Mark Abene wrote:

> I'd be hesitant to think the cross/mipsel toolchain is at fault, since plenty
> of other people are using it on this list, and the pica and olivetti people
> seem perfectly fine at last check (though the pica code doesn't use the L2
> cache, and the olivetti doesn't have one).

I am sorry for delay in writing this but if check in the mail archivesaround
Apr-june 2000 I HAD EXACTLY THE SAME PROBLEM
YOU HAVE NOW! (ie kernel forks init but printf added to main
don't display init seems to be sleeping etc. ONLY it was for NEC RISCserver
2200 )  If look later around July-August you will see some messages to the effect

that I got the kernel to work...

Now you're going to ask Bob  what did you do to make it work ? Well
the answer is I checkout out a later kernel release ( ie 3/30/2000
to July xx) ,added one patch (wrong calendar chip address)
and finally updated my compiler/binutil cross-build tools...
The changes to kernel source for arc during that period
were to buss-dma... but to this day I don't know if it was
just my build tools giving me grief or kernel source code modifications.

I was thinking about moving in your magnum changes
to the kernel source I use (1.5 Release not 1.5 current) building
it my mips arc machine to see what hapens...

Oh RiscServer use L2 cache (2 megs) but dcache line
size is 32 (not 16 like magnum).