RCS file: /cvsroot/syssrc/sys/arch/mips/mips/mips_machdep.c,v
retrieving revision 1.95
diff -u -C7 -r1.95 mips_machdep.c
*** mips_machdep.c      2000/07/20 18:33:42     1.95
--- mips_machdep.c      2000/07/27 04:33:44
***************
*** 664,677 ****
--- 664,678 ----
  {
        int szsigcode = pack->ep_emul->e_esigcode - pack->ep_emul->e_sigcode;
        struct frame *f = (struct frame *)p->p_md.md_regs;
  
        /*
         * Make sure sigreturn trampoline is coherent.
         */
+       *(volatile int *)p->p_sigacts->ps_sigcode; /* preload TLB entry */
  #ifdef MIPS3
        if (CPUISMIPS3)
                MachFlushDCache((vaddr_t)p->p_sigacts->ps_sigcode, szsigcode);
  #endif
        MachFlushICache((vaddr_t)p->p_sigacts->ps_sigcode, szsigcode);
        =================================================

This code behaves wrong for R3000 because the cache operations is
defined only for KSEG0.  That's the big incompability between R3000
and R4000 descenders which NetBSD/mips is yet to overcome in a sane
way.  MachFlush{I,D}cache() for R3000 take KSEG0 exclusively. 

Tohru Nishimura