On Thu, Jul 27, 2000 at 04:41:45PM +1200, Wayne Knowles wrote:

 > The problem is that a kuseg virtual address is being passed to
 > MachFlushICache in the setregs() function.   Under stressful conditions
 > the cache flushing routines can produce a TLB miss exception which has to
 > be handled by the high level TLB Exception functions.  Since the processor
 > is isolated from main memory at that stage weird things start to happen.

Hm, that's pretty Special.

 > All memory addresses passed to MachFlush{I,D}Cache should be kseg0 or
 > kseg1 addresses to ensure no TLB miss exceptions are generated during the
 > cache invalidation.

Is this true for MIPS-3?  I always forget if its I-cache is virtually
tagged, or not... Anyway...

 >   	/*
 >   	 * Make sure sigreturn trampoline is coherent.
 >   	 */
 > + 	*(volatile int *)p->p_sigacts->ps_sigcode; /* preload TLB entry */
 >   #ifdef MIPS3
 >   	if (CPUISMIPS3)
 >   		MachFlushDCache((vaddr_t)p->p_sigacts->ps_sigcode, szsigcode);
 >   #endif
 >   	MachFlushICache((vaddr_t)p->p_sigacts->ps_sigcode, szsigcode);

Try something like

	paddr_t sigcode_pa;

	.
	.
	.

	/*
	 * Make sure sigreturn trampoline is coherent.
	 */
#ifdef MIPS3
	if (CPUISMIPS3)
		MachFlushDCache((vaddr_t)p->p_sigacts->ps_sigcode, szsigcode);
#endif
	if (pmap_extract(p->p_vmspace->vm_map.pmap,
			 (vaddr_t)p->p_sigacts->ps_sigcode, &sigcode_pa))
		MachFlushICache(MIPS_PHYS_TO_KSEG0(sigcode_pa), szsigcode);

..but that's kinda ugly :-)

-- 
        -- Jason R. Thorpe <thorpej@zembu.com>