I have a question about MIPS processor writebuffer operation.

I heard that early implementation of R2000/R3000 processors had no
write buffer circuit inside to isolate CPU from memory subsystem.
There were companion chips for R2000/R3000 to implement write buffer.
Smart engineers could design their own memory control logic as a part
of 'system controller chip' for particular computer products.   This
is what Digital did for some of DS5000.

Newer designs of R3000 (A?) have write buffer circuit built inside
eliminating an external logics.  Now my question is; how such the
builtin WB can be drained?  I heard that WB drain can be done lw
operation of a 32bit quantity in KSEG1 space.

Tohru Nishimura