> > Software is responsible for configuration of MIPS3_CONFIG_SC bit
> > (secondary cache enable). And "#ifdef pmax" of the mips_machdep.c
> > seems to indicate that R4000 pmax's firemware doesn't initialize this
> > bit. Is this right?
> 
> No.
> 
> "MIPS R4000 User's Manual" clearly states that;
> 
> 	Some configuration options, as defined by Config bits 31:6, are
> 	set by the hardware during reset and are included in the Config
> 	register as read-only status bits for the software to access.
> 
> SC bit (MIPS3_CONFIG_SC) is bit 17, and read-only.

Oops. You are right. Thanks.

In other words, the following line in mips_machdep.c isn't needed.
	#ifdef pmax		/* XXX */
		mips_L2CachePresent = 1;	<-- this line
Could anyone who have R4000 pmax confirm this?

BTW, page 61 of Dominic Sweetman's "See MIPS Run" ("3.4.2 Config
Register: R4x00 Configuration") says:
	SC	In R4000 and R5000 CPUs and their immediate
		descendants, this field is writable and acts as a
		sofware-controlled enable for the secoundary cache;
Does anyone know the raitionale of this?
Is this description just wrong?
--
soda