>> Recently I reordered personal priority of mips_machdep.c rework in
>> order to remove any messy #ifdefs from the file contributing more
>> saner support of any funcy features found in new MIPS processors.  The
>> initial version for MIPS1 processors will appear soon.

The foundation and approach is derived from NetBSD/sparc,
encapsulation of [1] parameters specific to particular processor
implementations, [2] well coordinated code pieces for basic CPU
operations manipulating TLB (like TBIA, TBIS and others) and caches
(instruction/data, primary/ secondary, associativity and others) to be
useful building blocks for virtual memory subsystem and device drivers
including VDMA things found in some MIPS machines.

Subcomponents of locore might have another 'sw[]' like structure (they
may not be a part of CPU characteristics, but instance of how operating
system is implemented)

> Software is responsible for configuration of MIPS3_CONFIG_SC bit
> (secondary cache enable). And "#ifdef pmax" of the mips_machdep.c
> seems to indicate that R4000 pmax's firemware doesn't initialize this
> bit. Is this right?

No idea about it due to the lack of R4000 DECstation at hand.

The structure of mips_vector_init() is rather harmful than helpful so
as many who made MIPS porting have already experienced.

Tohru Nishimura