>> - some useful VM notions of RO, COW or defered modification attributes
>> could be implemented and manipulated by D bit of TLB entryhi register.
>> The D bit has many overlapped implications by the software managed MMU
>> architecture.  I can not figure out how the current code base handles
>> COW so far, but the right solution would be heavily coupled with
>> TLBmod exception handler.  Current code base is very fragile to be
>> 'corrected' and I've adandoned to 'improve' it.  trap() routine and
>> pmap.c are to be reworked (keeping multiprocessor mips64 in mind,
>> crossing fingers...)
>
> Sigh, I still owe you a message on how my approach to mod/ref works.

Two features, ASID (TLBPID) and G bit of TLB, are designed for the same
purposes of ASN and ASM found in Alpha processor.  (Icache management
differs in this aspect, interestingly)

Tohru Nishimura