>Ok, I just rewrote _bus_dmamap_sync() for the R3000 case, now that
>I have a better grip on how the caches work on the R3000 and R4000.
>
>Amusingly, my MIPS architecture manual says that the R{2,3}000 cache
>is _write-though_, so I am wondering why flushes are even necessary.
>Can someone enlighten me here?

Yes, it's a write-through cache, but there's no cache-coherency.

After doing a DMA input, you need to invalidate the footprint of the
DMA buffer (or used uncached addresses to access the buffer), or
cached reads might return stale cache footprint instead of the
newly-input data.

I forget the exact details for output. If writes to the DMA bnuffer
were uncached and the writebuffer is drained, then flushes aren't
necessary.  If there were cached writes to the DMA buffer, there may
be some short delay necessary to let dirty cache lines drain down to
DRAM.


>The R4000 case still needs some work, which I'll try and do this week; some
>data structure changes are going to be needed.  (mmm, virtually-indexed
>caches, gag.)

Yup.