Subject: Re: puc based 16550 on macppc?
To: Michael Lorenz <macallan@netbsd.org>
From: Joachim Thiemann <joachim.thiemann@gmail.com>
List: port-macppc
Date: 04/18/2007 12:56:10
On 18/04/07, Michael Lorenz <macallan@netbsd.org> wrote:
> > Do you want pcictl output as well?
> Actually that's what I wanted.
Oh, ok:
PCI configuration registers:
Common header:
0x00: 0x02001407 0x04800040 0x07000300 0x00000000
Vendor Name: Lava Semiconductor Manufacturing (0x1407)
Device ID: 0x0200
Command register: 0x0040
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: on
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Status register: 0x0480
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: slow (0x2)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: communications (0x07)
Subclass Name: serial (0x00)
Interface: 0x03
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x0000fff9 0x0000fff9 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x02001407
0x30: 0x00000000 0x00000000 0x00000000 0x00000100
Base address register at 0x10
type: i/o
base: 0x0000fff8, not sized
Base address register at 0x14
type: i/o
base: 0x0000fff8, not sized
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x1407
Subsystem ID: 0x0200
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Joe.