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Michael,

-> Hmm, gem always worked fine on my iBook G4 ( 800MHz model )
-> Please post dmesg and the gem's pcictl dump output, both of you.
->=20

Here's the output from pcictl:

$ /usr/sbin/pcictl pci2 list
000:11:0: Apple Computer UniNorth Host-PCI Bridge (host bridge)
000:15:0: Apple Computer GMAC Ethernet (ethernet network)

$ /usr/sbin/pcictl pci2 dump -d 15     =20
PCI configuration registers:
  Common header:
    0x00: 0x0021106b 0x84a00016 0x02000000 0x00001008

    Vendor Name: Apple Computer (0x106b)
    Device Name: GMAC Ethernet (0x0021)
    Command register: 0x0016
      I/O space accesses: off
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: on
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x84a0
      Capability List support: off
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: slow (0x2)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: on
    Class Name: network (0x02)
    Subclass Name: ethernet (0x00)
    Interface: 0x00
    Revision ID: 0x00
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x10
    Cache Line Size: 0x08

  Type 0 ("normal" device) header:
    0x10: 0xf5200000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x00000000
    0x30: 0xf5000000 0x00000000 0x00000000 0x40400129

    Base address register at 0x10
      type: 32-bit nonprefetchable memory
      base: 0xf5200000, not sized
    Base address register at 0x14
      not implemented(?)
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x0000
    Subsystem ID: 0x0000
    Expansion ROM Base Address: 0xf5000000
    Reserved @ 0x34: 0x00000000
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x40
    Minimum Grant: 0x40
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x29

  Device-dependent header:
    0x40: 0x00000000 0x00000000 0x00000000 0x00000000
    0x50: 0x00000000 0x00000000 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x00000000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000


Thanks for looking into this.

Allen
--=20
Documentation is alot like sex.  When it's good, it's very, very good.  And
when it's bad, it's still better than nothing.
 7:20PM  up 20 days, 23:41, 1 user, load averages: 0.39, 0.21, 0.15

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