John Klos wrote:
>> At least on the MPC74[45-57] (G4 family), your change would be fine;
>> dcbi and dcbf are supposed to be identical except that dcbi is a
>> privelged instruction. I don't see any indication that it's a problem,
>> though - this seems like a G2-core-specific issue.
> 
> 
> Does anyone see any reason to not commit this change? I've read what I 
> can about dcbi versus dcbf, and it seems that dcbf is more appropriate, 
> anyway. I'm not entirely sure of all of the instances where DMA is going 
> on when we arrive at BUS_DMASYNC_POSTREAD, but I think it's pretty safe 
> to assume that we'd never even theoretically have an instance where 
> another DMA operation is changing data that matches a cache line that 
> was part of what was going on with the DMA operation that resulted in 
> ending up at BUS_DMASYNC_POSTREAD. Therefore, writing back to memory 
> should never be an issue.

The point of using dcbi is prevent a writeback of potentially stale
data.  And to avoid an unneeded memory write.  As the person responsible
for that code, I would rather have the init code rewrite the dcbi
instructions to dcbf just for G2 processors.  (we already have code that
does that for AltiVec and other things).

> Am I understanding this wrong, or should we never have a problem 
> flushing a cache line when we get to BUS_DMASYNC_POSTREAD?

Only if there hasn't been a memory reference to that cacheline
since the PREREAD has been done.
-- 
Matt Thomas                     email: matt@3am-software.com
3am Software Foundry              www: http://3am-software.com/bio/matt/
Cupertino, CA              disclaimer: I avow all knowledge of this message.