Hello,

> Level signaling means that each device holds the line asserted until it has been
> serviced - they are effectively OR'd together.  Another interrupt won't be generated
> until the interrupt is deasserted, which only happens when all devices sharing the
> IRQ are simultaneously not asserting it.  This is not guaranteed to happen at any
> time since each handler can only clear one of the inputs to the "OR gate".  Polling
> the line and seeing it deasserted is the only way to ensure the GC's latch has been
> reset so it can generate the interrupt again.
Well, in this case we should probably check the IRQ registers in do_pending_intr() and keep looping until the line goes down, but this may cause other problems.
Moving gc_enable_irq behind the handlers ( or at least behind the part that clears the pending bit ) should do that - it would loop through the handlers until the line goes down which may take forever, so it may be a good idea to defer it until we get the next clock interrupt after a couple of loops to avoid a deadlock...

have fun
Michael