Subject: Re: 604e vs. 604ev (was Re: results of the IRC debug patch)
To: Brian Hechinger <wonko@4amlunch.net>
From: Michael <macallan18@earthlink.net>
List: port-macppc
Date: 12/06/2004 07:53:28
Hello,
> > > I also swap CPUs from time to time and
> > > I'd rather have the L2 configuring not hard coded into the kernel.
> > Sure. I only did it because it was the only way to get the L2 cache enabled at all.
>
> hey, how do i enable L2 cache by hand in the kernel? and what do i need to know
> to get it setup right? it's a 400Mhz Sonnet G3 card.
Figure out the cache's size and clock ratio, then add something like this to your kernel config ( and config, make depend, make... )
options L2CR_CONFIG="(L2SIZ_1M|L2CLK_20|L2RAM_PIPELINE_BURST)"
This is what I did for my 300MHz G3 with 1MB cache at 150MHz, so clock ratio is 2, there are other macros for different sizes...
#define L2SIZ_256K 0x10000000
#define L2SIZ_512K 0x20000000
#define L2SIZ_1M 0x30000000
... ratios ...
#define L2CLK_DIS 0x00000000 /* disable L2 clock */
#define L2CLK_10 0x02000000 /* core clock / 1 */
#define L2CLK_15 0x04000000 /* / 1.5 */
#define L2CLK_35 0x06000000 /* / 3.5 */
#define L2CLK_20 0x08000000 /* / 2 */
#define L2CLK_25 0x0a000000 /* / 2.5 */
#define L2CLK_30 0x0c000000 /* / 3 */
#define L2CLK_40 0x0e000000 /* / 4 */
... and types...
#define L2RAM_FLOWTHRU_BURST 0x00000000
#define L2RAM_PIPELINE_BURST 0x01000000
#define L2RAM_PIPELINE_LATE 0x01800000
have fun
Michael