on 2/13/03 2:31 PM, Cliff Neighbors at cliff@allegronetworks.com wrote:

> this won't work unless all access to `ipending' also use lwarx/stwcx
> otherwise you will not detect and avoid the race.

That's what the code does.

> void
> softintr(ipl)
>   int ipl;
> {
>   u_int scratch;
>   asm volatile (
>       "1:  lwarx  %0, 0, %1;"
>           "or     %0, %0, %2;"
>           "stwcx. %0, 0, %1;"
>           "bne- 1b;"
>           : "+r"(scratch) : "r"(&ipending), "r"(1 << ipl));
> }

The function compiles to:

00350350 <softintr>:
  350350:       3d 20 00 4f     lis     r9,79
  350354:       38 00 00 01     li      r0,1
  350358:       7c 00 18 30     slw     r0,r0,r3
  35035c:       39 29 ac b8     addi    r9,r9,-21320
  350360:       7d 60 48 28     lwarx   r11,r0,r9
  350364:       7d 6b 03 78     or      r11,r11,r0
  350368:       7d 60 49 2d     stwcx.  r11,r0,r9
  35036c:       40 a2 ff f4     bne-    350360 <softintr+0x10>
  350370:       4e 80 00 20     blr


r9 is loaded with the _address_ of ipending.  The lwarx loads from this
address and the stwcx stores back to it.

-- monroe
------------------------------------------------------------------------
Monroe Williams                                         monroe@pobox.com