Re: arch/mac68k/obio/esp.c and resetting DRQ

[Rin Okuyama <rokuyama.rk%gmail.com@localhost>]

Hi,

Sorry for the late reply.

esp(4) actually works on my Q800.

That DREQ bit is cleared in via2_intr():

https://nxr.netbsd.org/xref/src/sys/arch/mac68k/mac68k/via.c#via2_intr

So, it is not always on after any SCSI interrupt.

As you pointed out, it is not cleared in esp(4) driver itself. As a result,
via2_intr() may unnecessarily call esp_intr() for the next time. However,
still, this does not cause serious problems (except for small performance
penalty); esp_intr() rejects such a spurious interrupt:

https://nxr.netbsd.org/xref/src/sys/arch/mac68k/obio/esp.c#esp_intr

I've tried this patch:

https://gist.github.com/rokuyama/e22f2a5c9d5d963ba3d3ba10615c0293

to observe what is going on my Q800. The result after multiuser boot is
something like:

----
q800# vmstat -ev | grep esp
esp spurious                                          2593    3 trap
esp dreq1                                                2    0 trap
esp dreq0                                               33    0 trap
----

Here, "spurious" counter increases with disk I/O whereas "dreq[01]" are
(almost?) unchanged.

I've also tested the patch above on Q840AV, where "quick DMA" routines
are not used. Then, "spurious" counter is zero after multiuser boot.

It may be better to turn off this DREQ bit in somewhere in "quick DMA"
routines. However, I don't know where should be, at the moment. (It is
not esp_have_dreq(); these functions are rarely called as suggested
above.)

Thanks,
rin

On 2022/01/18 5:52, Mark Cave-Ayland wrote:
> Hi all,
>
> I've been looking at arch/mac68k/obio/esp.c to try and understand how the SCSI DRQ signal gets reset on a Q800 and wonder if anyone has any real hardware or relevant experience. The background to this is that I'm working on a set of patches for QEMU that will enable the Q800 machine to boot MacOS, NetBSD and A/UX.
>
> According to the GTTMFH the SCSI DRQ signal is connected to the CA2 control line in VIA2 (bit 0 in the IFR) and therefore this bit should be latched until either port A is read from/written to (input mode) or bit 0 is reset in the IFR (independent mode) by writing a 1.
>
> However esp_iosb_have_dreq() simply checks bit 0 of the IFR "live" to look for DRQ and I don't see any writes to back to the IFR or accesses from VIA2 port A to reset the flag in IFR once again. This would suggest that using this code DRQ would always remain set after any SCSI IO.
>
> Does anyone have any more detail as to how this mechanism works on real hardware? I'd be interested to know if esp_iosb_have_dreq() ever returns a value for the DRQ bit that isn't 1.
>
>
> Many thanks,
>
> Mark.