On Tue, 25 May 1999, Matthew Navarre wrote:

> Frederick Bruckman wrote:
> >Good luck. The PowerMac is of completely different architecture than
> >the Quadras. Uh... different chip, too. 680xx's don't have registers
> >for interrupts, and that's just the beginning: it's considered a CISC
> >design--powerpc is RISC. You could try posting your question to the
> >low-volume macppc mailing list. You might also try one of the
> >comp.sys.powerpc* newsgroups.
> 
> The 5200/5260 at least are essentially Quadra 630's with a PPC accelerator.

That pretty much coincides with my info, except the model number, which I
didn't have a clue about.  Thanks for the info there.  :-)


> The hardware map in Apples hardware docs for these is the same as the 630
> with a PPC processor and a chip to translate between the 603/603e and the
> mc68040 bus. I can't remember the url offhand but I recently found the
> hardware documents for both machines on Apples web site

Same thing for the 53/52/5300 series machines.  Basically, it's an
accelerated Quadra with a bus translation unit of some ilk.  I think I
have all of Apple's publicly available PDF files, including some info
about the VIA locations and stuff.  What I don't know is if there's a VIA
register (or perhaps a register on the bus bridge... hmm...) into which
the other VIA interrupts (and one other chip)  cascade.  Anybody?

IOW, I guess the question is: how many different VIA registers (ports,
whatever) does the Quadra interrupt handling code have to read at the
first stage?  Does it read several, each of which cascade into others, or
does it read a single one, which cascades into several, which cascade into
others?


Later,
David

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