On Tue, 25 May 1999, David A. Gatwood wrote:

> Is anyone out there particularly familiar with the Quadras?  I'm trying to
> figure out interrupt handling for the PowerMac (or Performa) 52/53/62/63xx
> series, which should be closely related to some Quadra models (I have no
> idea which ones except that it's non-DMA-capable, if that helps).  On the
> later PowerMacs, there's a master interrupt control/flag register pair
> into which all of the other interrupts are cascaded.  Is there anything
> similar in the Quadras?  If not, is there anything in particular that
> needs to be done to cause the IRQ line to go low or whatever after you've
> read the interrupts from one of the interrupt flag registers?  Anybody?

Good luck. The PowerMac is of completely different architecture than
the Quadras. Uh... different chip, too. 680xx's don't have registers
for interrupts, and that's just the beginning: it's considered a CISC
design--powerpc is RISC. You could try posting your question to the
low-volume macppc mailing list. You might also try one of the
comp.sys.powerpc* newsgroups.