On Sun, 3 Mar 1996, Allen Briggs wrote:

> > If we used true DMA, I'd agree. But aren't we doing pseudo DMA?
> > Thus all data went through the CPU, so the cache should have
> > seen Process B get paged in, as the CPU did it?
> 
> Hmm...  You are right...  The memory would have to go through the CPU
> to the physical addresses.  I'm not sure when it's necessary to flush
> the cache, now...

It's been a long time since I had to deal with this, so this may be a little
off, but here's another reason that the cache may need to be flushed:

  The kernel is paging executable code into memory due to a context switch.
  Remembering that the 030 has separate data and instruction caches, the
  memory that is filled with the new "process" won't be cached in the 
  _instruction_ cache, because as it is filled it is _data_. Then the
  kernel switches to actually running that process. The CPU
  instruction cache may now contain invalid data because if it was holding
  instruction data from the same address it just loaded then it was 
  not updated because it was loaded as "data".

	--John

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 John Wittkoski				InSoft, Inc.
 Senior Systems Engineer                Phone: (717) 730-9501
 Email: jpw@insoft.com                  Fax  : (717) 730-9504
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