I could easily be wrong on this, but if I am, please tell me where to
look for proof...  ;-)

> > Think on it a bit longer.  Consider the following scenario:
> > 	Process A stores something in the page at virtual address 0 at
> > 		physical address 0x00040000
> > 	Process B is switched in and pages in virtual address 0x10000 at
> > 		physical address 0x00040000
> > If the caches aren't flushed, process B could see the cached contents
> > from process A's virtual address 0.
> 
> If we used true DMA, I'd agree. But aren't we doing pseudo DMA?
> Thus all data went through the CPU, so the cache should have
> seen Process B get paged in, as the CPU did it?

Hmm...  You are right...  The memory would have to go through the CPU
to the physical addresses.  I'm not sure when it's necessary to flush
the cache, now...

> Also, how is the cache told not to cache IO addresses?

By bits in the page table.  There are "cache mode" bits and these are
set to "cache-inhibit" for the I/O space (see pmap_bootstrap.c).

-allen

-- 
  Allen Briggs - end killing - briggs@bev.net ** MacBSD == NetBSD/mac68k **
   Where does all my time go?  <a href="http://www.netbsd.org/">Guess.</a>