m68k cacheops header -- some questions

[Jason Thorpe <thorpej%me.com@localhost>]

Hey folks,

Some questions about the m68k cacheops header:

1. The TBIS (TLB-invalidate-single) always operate on the user and supervisor side.  Is it worth having separate USER vs KERN versions of these operations to support systems that can do it (which I think includes the ‘851, ‘030, ‘040, and ‘060)?  Obviously the HP MMU doesn’t get to have this optimization.  Wildcard: I’m not certain what happens with the D-cache on the ‘030 (are the cache lines tagged with the function code?  I need to re-read the manual I guess…)

2. What’s the difference between ICIA and ICPA?  As far as I can tell, they’re equivalent within each CPU+MMU tuple.

3. What’s with PCIA_20?  It uses the CACR, but the 68020 doesn’t have an on-chip D-cache, right?

4. Ditto with PCIA_30?  The name implies “physical”, which of course the 68030 D-cache is not.  I suppose this is there as a fall through for 68030 systems with external phys caches (if we’re invalidating the external cache, we should invalidate the internal one, too).  Just confirming.

5. If so, why don’t we just have a single DCIA_30?

6. Why on earth doesn’t the m68k bus_dma invalidate the D-cache in the PREREAD (or POSTREAD, since the cache is write-through) case?

-- thorpej