FPU exceptions don't report a siginfo code

[Martin Husemann <martin%duskware.de@localhost>]

While testing src/regress/lib/libc/ieeefp/except, I noticed that m68k ports
don't fill in the si_code member of the siginfo passed. The solution should
be applied to all m68k ports, but I'd like to get some review first:

Index: trap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mac68k/mac68k/trap.c,v
retrieving revision 1.132
diff -c -u -r1.132 trap.c
--- trap.c      3 Dec 2007 15:33:54 -0000       1.132
+++ trap.c      9 Jan 2008 14:36:50 -0000
@@ -269,6 +269,22 @@
        userret(l, f, t, 0, 0);
 }
 
+static u_int
+fpsr2siginfocode(u_int fpsr)
+{
+       if (fpsr & (1 << 10))
+               return FPE_FLTDIV;
+       if (fpsr & (1 << 11))
+               return FPE_FLTUND;
+       if (fpsr & (1 << 12))
+               return FPE_FLTOVF;
+       if (fpsr & (1 << 13))
+               return FPE_FLTINV;
+       if (fpsr & (1 << 9))
+               return FPE_FLTRES;
+       return 0;
+}
+
 /*
  * Trap is called from locore to handle most types of processor traps,
  * including events such as simulated software interrupts/AST's.
@@ -408,8 +424,9 @@
                 * 3 bits of the status register are defined as 0 so
                 * there is no clash.
                 */
+               ksi.ksi_code = v;
                ksi.ksi_signo = SIGFPE;
-               ksi.ksi_addr = (void *)code;
+               ksi.ksi_code = fpsr2siginfocode(code);
                break;
 
        /*


The fpsr2siginfocode() function should be shared. Any archs that can not
use it?

I guess there probably are usable definitions for the exception bits,
so we should use those - but I didn't find them.

Could someone please explain the comment about 3 bits/clashing - I did
not understand it at all and think it probably should just be deleted,
as it describes the pre-siginfo implementation.

Martin