Todd Vierling wrote:
> 
[ ..... ]
> I hate to think interrupts should ever need to be locked out in such
> situations, but you're right in that not every processor is uninterruptible
> like this.  And then again, the compiler may not even decide to compile it
> that way.  (It might decide to do a BTST followed by BSET/BCLR for one bit
> of this on a m68k; that's certainly interruptible.)  Given that this code is
> running in supervisor mode, if code spawned by interrupts doesn't access
> this data, no lock worries.  If the point is to worry about interrupts...
> <cringe>
It might be a good idea to retreat to the source of this thread. It was taken
to port-m68k in the middle of the discussion. The decision to take it to this
list is right, but a short description of my original post might be
worthwhile :-)
What I wanted to do was provide macro's named single_instruction_bset/bclr that 
provided a compiler independent (for the reason you mentioned above) way of
setting/clearing bits in a single instruction. The current gcc version uses
a 3 instruction sequence for this when manipulation a volatile variable.
These macro;s would allow me to manipulate things like interrupt registers
without guarding them by spl-calls - this is a waste like you said above.
Note that guarding is needed as soon as a second processor is used.

The macro's look like:

    #define single_instruction_bset(var, bit, size)	\
       asm volatile ("or" __STRING(size) " %0,%1" : : "di"(bit), "g"(var))

I'm planning to add these macro's to m68k/include/asm_single.h unless
someone shoots enough holes in this idea ;-)

Leo.