I've added some instrumentation to the NetBSD kernel that indicates
PCI exceptions detected by the AMD Elan SC520 processor on the Soekris
net4521.  At boot, I see a PCI Master Abort for a PCI Memory Read from
the physical address 0x470:

elansc_attach: MMCR_PICICR 03
elansc_attach: MMCR_MPICMODE 02
elansc_attach: interrupting at irq 1
elansc_attach: MMCR_ADDDECCTL 90
gpio0 at elansc0: 32 pins
cbb0 at pci0 dev 17 function 0: vendor 0x104c product 0xac51 (rev. 0x00)
cbb1 at pci0 dev 17 function 1: vendor 0x104c product 0xac51 (rev. 0x00)
sip0 at pci0 dev 18 function 0: NatSemi DP83815 10/100 Ethernet, rev 00
sip0: interrupting at irq 11
sip0: Ethernet address 00:00:24:c0:73:3c
nsphyter0 at sip0 phy 0: DP83815 10/100 media interface, rev. 1
nsphyter0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
sip1 at pci0 dev 19 function 0: NatSemi DP83815 10/100 Ethernet, rev 00
sip1: interrupting at irq 5
sip1: Ethernet address 00:00:24:c0:73:3d
nsphyter1 at sip1 phy 0: DP83815 10/100 media interface, rev. 1
nsphyter1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
cbb0: enabling read bursts
cbb0: interrupting at irq 10
cardslot0 at cbb0 slot 0 flags 0
cardbus0 at cardslot0: bus 1
pcmcia0 at cardslot0
cbb1: interrupting at irq 10
cardslot1 at cbb1 slot 1 flags 0
cardbus1 at cardslot1: bus 2
pcmcia1 at cardslot1
isa0 at mainbus0  
com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, working fifo
com0: console
com1 at isa0 port 0x2f8-0x2ff irq 3: ns16550a, working fifo
wdc0 at isa0 port 0x1f0-0x1f7 irq 14
atabus0 at wdc0 channel 0
npx0 at isa0 port 0xf0-0xff
elan_intr: enter  
elan_intr: memory rd 00000470 master abort
cmos: attached.

Does anyone know where that read comes from?  I have not found it by
grepping the sources.

According to
<http://heim.ifi.uio.no/~stanisls/helppc/bios_data_area.html>, at 0x470
is the "clock rollover flag" in the BIOS memory area, at 0x471 is the
"BIOS break flag," and at 0x472 is the "soft reset flag".

I suppose it is possible that either the BIOS, the 1st- or 2nd-stage
bootloader read 0x470, and the CPU interrupts us later.  The kernel
installs its interrupt handler for the PCI exceptions way before the
exception occurs, however.

Dave

-- 
David Young             OJC Technologies
dyoung@ojctech.com      Urbana, IL * (217) 278-3933 ext 24