On Fri, Sep 09, 2005 at 08:57:09PM +0200, Frank van der Linden wrote:
> Manuel Bouyer wrote:
> 
> The 32 limit in the x86 interrupt code is the number of unique interrupt 
> sources (i.e. not shared), per CPU.

So it's not the interrupt number printed in dmesg, on lines such as:
uhci3: interrupting at irq 10

> I've not seen situations where that 
> isn't enough in practice.
> 
> The interrupt numbers themselves can be higher, that's no problem (see 
> e.g. the is_pin value in the intr_source structure). I don't know 
> exactly what the NetBSD/xen interrupt code does, glancing at it, it 
> looks like a modified version of the x86 code.

Xen uses "event channels" as interrupts, these are generated by the
hypervisor. There can be up to 1024 event channels per domain.
When a domain has access to physical hardware, it ask the hypervisor
to do a assign an event channel to the physical interrupt (physical
interrupt being the number read in the PCI interrupt register, or
specified in the kernel config file for ISA devices).
In NetBSD/Xen there is a table that keep track of physical interrupt to
event channel mapping. Here I assumed that a physical interrupt number would
not be greather than 31, but if I understood it properly, it can be up to
255.

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
     NetBSD: 26 ans d'experience feront toujours la difference
--