Subject: x86 "lock" in assebly [Re: x86 instructions reordering]
To: None <>
From: Manuel Bouyer <>
List: port-i386
Date: 03/25/2005 23:53:41
Hi again
thanks to all who replied. From what I've learned here, and after re-reading
the code, there are possible races in the event code itelf that could
cause events to be missed, in the multiprocessor case with instruction
reordering by the processors.
I tried to insert "lock;" instructions in sensible places in the assembly,
but it seems that not all instructions can have a lock prefix.
If I put a lock before a movb or a testb, the assembler doesn't complain but
the kernel panics with a "privileged instruction fault trap" on the
Does it mean that these instructions can't be reordered by the CPU, so the
lock prefix doesn't make sense ?
If not, I guess a 
addl $0, 0(%esp)
would work (this is what x86_lfence() does) ?

Manuel Bouyer <>
     NetBSD: 26 ans d'experience feront toujours la difference