That is extremely interesting. I think you must be right about the L2
cache being disabled. Below are my results from running heapsort on the
2.4 GHz Xeon.


   Heap Sort C Program
   Version 1.0, 04 Oct 1992

   Size of long (bytes): 4

   Array Size    RunTime      Scale    MIPS
    (bytes)       (sec)
         8000     0.0087     0.4202   48.19
        16000     0.0192     0.9087   47.23
        32000     0.0402     1.9536   48.62
        64000     0.0900     4.1799   46.46
       128000     0.1929     8.9025   46.15
       256000     0.4133    18.8884   45.70
       512000     0.8734    39.9503   45.74
      1024000     1.8513    84.2432   45.51
      2048000     3.8544   177.1721   45.97

   Runtime is the average for 1 iteration.
   High MIPS =    48.62
   Low  MIPS =    45.51


For comparison I also ran heapsort on my 1.5 GHz P4 system and the
results are as following:


   Heap Sort C Program
   Version 1.0, 04 Oct 1992

   Size of long (bytes): 4

   Array Size    RunTime      Scale    MIPS
    (bytes)       (sec)
         8000     0.0006     0.4202  723.65
        16000     0.0013     0.9087  723.14
        32000     0.0026     1.9536  755.06
        64000     0.0054     4.1799  767.91
       128000     0.0118     8.9025  752.65
       256000     0.0239    18.8884  790.21
       512000     0.0641    39.9503  623.25
      1024000     0.1709    84.2432  493.00
      2048000     0.4880   177.1721  363.07

   Runtime is the average for 1 iteration.
   High MIPS =   790.21
   Low  MIPS =   363.07


It makes a good bit of sense that it could be the issue. Now the
question is how does it get fixed? Thank you so much for your help.

Bryan