Subject: Re: Net4801 probe
To: None <nathanw@wasabisystems.com>
From: Jun-ichiro itojun Hagino <itojun@itojun.org>
List: port-i386
Date: 08/19/2003 07:41:12
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> > here's openbsd's dmesg. it apparently touches function 1 of
> > SC1100 device, but does not panic like netbsd does.
> Digging deeper into the SC1100 manual, I found an interesting
> register. Page 169 of SC1100.pdf from National Semiconductor:
>
> "Table 5-29. F0: PCI Header and Bridge Configuration for GPIO and LPC
> Support
>
> Index 41h PCI Function Control Register 2 (R/W) Reset Value: 00h
>
> Bit Description
> ...
> 1 Power Management Configuration Trap.
> If this bit is set to 1 and an access occurs to one of the
> configuration resisters in PCI function 1 (F1) register space,
> an SMI is generated."
>
> (other bits exist to trap accesses to IDE (F2), "XpressAUDIO" (F3),
> and legacy ISA I/O space).
>
> Given the existence of this register, it seems possible that NetBSD is
> setting (or OpenBSD and FreeBSD are clearing) that bit, or perhaps are
> set up to handle SMI differently. A little code in
> sys/arch/i386/pci/pchb.c or, if it's booted, "pcictl /dev/pci0 dump -d
> 0 -f 0" would be informative.
attached output when booted with "skip function 1" quirk.
yes, offset 0x41 has bit 1 set, i.e. SMI gets generated if function 1
is touched. hmm, should we clear the bit in
sys/arch/i386/i386/identcpu.c? or is it a BIOS issue? are there any
people having the similar simptom with non-soekris4801 machines w/
SC1100 CPU?
itojun
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PCI configuration registers:
Common header:
0x00: 0x00011078 0x02800107 0x06000000 0x00001f00
Vendor Name: Cyrix Corporation (0x1078)
Device Name: MediaGX Built-in PCI Host Controller (0x0001)
Command register: 0x0107
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): on
Fast back-to-back transactions: off
Status register: 0x0280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: host (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x1f
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x41001c0e 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
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