Subject: Re: built-in wi on sony vaio
To: Manuel Bouyer <bouyer@antioche.lip6.fr>
From: Kurt Schreiner <ks@ub.uni-mainz.de>
List: port-i386
Date: 03/26/2003 16:12:56
Hi Manuel,
the problem is the PCI Interrupt Router reported by the BIOS:
there's no 82371FB in there (which doesn't know about the additional
interrupts provided by the 830MP) but an Intel 82801CAM LPC
Interface providing 8 interrupts. (Why is the BIOS lying?)
I've done the attached "really cruel hack"(TM) to get the wi in my
Toshiba Tecra9000 up and running.
There may be more elegant solutions, but this makes the wi usable, so
for me it's ok... ;-)
May be this can help to get your Vaio more usable, too...
-Kurt
diff -ru --unidirectional-new-file /usr/src/sys/arch/i386/pci/pci_intr_fixup.c /u/NetBSD/lsrc/sys/arch/i386/pci/pci_intr_fixup.c
--- /usr/src/sys/arch/i386/pci/pci_intr_fixup.c 2003-02-27 16:47:04.000000000 +0100
+++ /u/NetBSD/lsrc/sys/arch/i386/pci/pci_intr_fixup.c 2003-02-27 22:46:36.000000000 +0100
@@ -143,6 +143,8 @@
piix_init },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC,
piix_init },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC,
+ piix2_init },
{ PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558,
opti82c558_init },
diff -ru --unidirectional-new-file /usr/src/sys/arch/i386/pci/pci_intr_fixup.h /u/NetBSD/lsrc/sys/arch/i386/pci/pci_intr_fixup.h
--- /usr/src/sys/arch/i386/pci/pci_intr_fixup.h 2001-08-27 10:21:21.000000000 +0200
+++ /u/NetBSD/lsrc/sys/arch/i386/pci/pci_intr_fixup.h 2002-08-20 13:23:22.000000000 +0200
@@ -55,6 +55,8 @@
*/
int piix_init __P((pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
pciintr_icu_tag_t *, pciintr_icu_handle_t *));
+int piix2_init __P((pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
+ pciintr_icu_tag_t *, pciintr_icu_handle_t *));
int opti82c558_init __P((pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
pciintr_icu_tag_t *, pciintr_icu_handle_t *));
int opti82c700_init __P((pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
diff -ru --unidirectional-new-file /usr/src/sys/arch/i386/pci/pcibios.c /u/NetBSD/lsrc/sys/arch/i386/pci/pcibios.c
--- /usr/src/sys/arch/i386/pci/pcibios.c 2003-02-27 16:47:04.000000000 +0100
+++ /u/NetBSD/lsrc/sys/arch/i386/pci/pcibios.c 2003-02-27 22:42:39.000000000 +0100
@@ -294,6 +294,11 @@
pcibios_pir_header.router_bus,
PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc),
PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc));
+#if defined(TOSHI) && TOSHI == 0x9000
+ printf("\npcibios_pir_init: resetting compat_router from 0x%x to 0x248c8086\n",
+ pcibios_pir_header.compat_router);
+ pcibios_pir_header.compat_router = 0x248c8086;
+#endif
if (pcibios_pir_header.compat_router != 0) {
pci_devinfo(pcibios_pir_header.compat_router, 0, 0,
devinfo);
diff -ru --unidirectional-new-file /usr/src/sys/arch/i386/pci/piix.c /u/NetBSD/lsrc/sys/arch/i386/pci/piix.c
--- /usr/src/sys/arch/i386/pci/piix.c 2003-03-05 17:54:17.000000000 +0100
+++ /u/NetBSD/lsrc/sys/arch/i386/pci/piix.c 2003-02-27 22:52:18.000000000 +0100
@@ -161,10 +161,10 @@
/*
* XXX Pattern 3: configuration register offset 1
- * Some BIOS return 0x68, 0x69
+ * Some BIOS return 0x68, 0x69, 0x6a, 0x6b
*/
- if (link >= 0x68 && link <= 0x69) {
- *clinkp = link - 0x67;
+ if (link >= 0x68 && link <= 0x6b) {
+ *clinkp = link - 0x60;
DPRINTF(("PIRQ %d (register offset 1)\n", *clinkp));
return (0);
}
diff -ru --unidirectional-new-file /usr/src/sys/arch/i386/pci/piix2.c /u/NetBSD/lsrc/sys/arch/i386/pci/piix2.c
--- /usr/src/sys/arch/i386/pci/piix2.c 1970-01-01 01:00:00.000000000 +0100
+++ /u/NetBSD/lsrc/sys/arch/i386/pci/piix2.c 2003-02-27 23:05:57.000000000 +0100
@@ -0,0 +1,333 @@
+/* $NetBSD: piix.c,v 1.5 2003/02/26 22:23:10 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1999, by UCHIYAMA Yasushi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the developer may NOT be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Support for the Intel PIIX2 PCI-ISA bridge interrupt controller.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: piix.c,v 1.5 2003/02/26 22:23:10 fvdl Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <machine/intr.h>
+#include <machine/bus.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
+
+#include <i386/pci/pci_intr_fixup.h>
+#include <i386/pci/piix2reg.h>
+#include <i386/pci/piix2var.h>
+
+/*
+#define PIIX2_DEBUG 1
+ */
+
+#ifdef PIIX2_DEBUG
+#define DPRINTF(arg) printf arg
+#else
+#define DPRINTF(arg)
+#endif
+
+int piix2_getclink __P((pciintr_icu_handle_t, int, int *));
+int piix2_get_intr __P((pciintr_icu_handle_t, int, int *));
+int piix2_set_intr __P((pciintr_icu_handle_t, int, int));
+#ifdef PIIX2_DEBUG
+void piix2_pir_dump __P((struct piix2_handle *));
+#endif
+
+const struct pciintr_icu piix2_pci_icu = {
+ piix2_getclink,
+ piix2_get_intr,
+ piix2_set_intr,
+ piix2_get_trigger,
+ piix2_set_trigger,
+};
+
+int
+piix2_init(pc, iot, tag, ptagp, phandp)
+ pci_chipset_tag_t pc;
+ bus_space_tag_t iot;
+ pcitag_t tag;
+ pciintr_icu_tag_t *ptagp;
+ pciintr_icu_handle_t *phandp;
+{
+ struct piix2_handle *ph;
+
+ ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
+ if (ph == NULL)
+ return (1);
+
+ ph->ph_iot = iot;
+ ph->ph_pc = pc;
+ ph->ph_tag = tag;
+
+ if (bus_space_map(iot, PIIX2_REG_ELCR, PIIX2_REG_ELCR_SIZE, 0,
+ &ph->ph_elcr_ioh) != 0) {
+ free(ph, M_DEVBUF);
+ return (1);
+ }
+
+#ifdef PIIX2_DEBUG
+ piix2_pir_dump(ph);
+#endif
+ *ptagp = &piix2_pci_icu;
+ *phandp = ph;
+ return (0);
+}
+
+int
+piix2_getclink(v, link, clinkp)
+ pciintr_icu_handle_t v;
+ int link, *clinkp;
+{
+ DPRINTF(("PIIX2 link value 0x%x: ", link));
+
+ /* Pattern 1: simple. */
+ if (PIIX2_LEGAL_LINK(link - 1)) {
+ *clinkp = link - 1;
+ DPRINTF(("PIRQ %d (simple)\n", *clinkp));
+ return (0);
+ }
+
+ /* Pattern 2: configuration register offset */
+ if ( (link >= 0x60 && link <= 0x63) ||
+ (link >= 0x68 && link <= 0x6b) ) {
+ *clinkp = link - 0x60;
+ DPRINTF(("PIRQ %d (register offset)\n", *clinkp));
+ return (0);
+ }
+
+ DPRINTF(("bogus IRQ selection source\n"));
+ return (1);
+}
+
+int
+piix2_get_intr(v, clink, irqp)
+ pciintr_icu_handle_t v;
+ int clink, *irqp;
+{
+ struct piix2_handle *ph = v;
+ int shift;
+ pcireg_t reg;
+/*
+printf("\npiix2_get_intr: clink=0x%x\n", clink);
+ */
+
+ if (PIIX2_LEGAL_LINK(clink) == 0)
+ return (1);
+
+ if (PIIX2_LEGAL_LINK_60(clink)) {
+ reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ);
+ shift = clink << 3;
+/*
+printf("\npiix2_get_intr/60: reg=0x%x\n", reg);
+printf("\npiix2_get_intr/60: clink<<3=0x%x\n", shift);
+printf("\npiix2_get_intr/60: reg>>shift=0x%x\n", reg >> shift);
+ */
+ if ((reg >> shift) & PIIX2_CFG_PIRQ_NONE)
+ *irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION;
+ else
+ *irqp = PIIX2_PIRQ(reg, clink);
+ } else {
+ if (PIIX2_LEGAL_LINK_68(clink)) {
+ reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ1);
+ shift = clink << 3;
+/*
+printf("\npiix2_get_intr/68: reg=0x%x\n", reg);
+printf("\npiix2_get_intr/68: clink<<3=0x%x\n", shift);
+printf("\npiix2_get_intr/68: reg>>shift=0x%x\n", reg >> shift);
+ */
+ if ((reg >> shift) & PIIX2_CFG_PIRQ_NONE)
+ *irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION;
+ else
+ *irqp = PIIX2_PIRQ(reg, clink);
+ }
+ }
+ return (0);
+}
+
+int
+piix2_set_intr(v, clink, irq)
+ pciintr_icu_handle_t v;
+ int clink, irq;
+{
+ struct piix2_handle *ph = v;
+ int shift;
+ pcireg_t reg;
+
+ if (PIIX2_LEGAL_LINK(clink) == 0 || PIIX2_LEGAL_IRQ(irq) == 0)
+ return (1);
+
+ if (PIIX2_LEGAL_LINK_60(clink)) {
+ reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ);
+ shift = clink << 3;
+ reg &= ~((PIIX2_CFG_PIRQ_NONE | PIIX2_CFG_PIRQ_MASK) << shift);
+ reg |= irq << shift;
+ pci_conf_write(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ, reg);
+ } else {
+ if (PIIX2_LEGAL_LINK_68(clink)) {
+ reg = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ1);
+ shift = clink << 3;
+ reg &= ~((PIIX2_CFG_PIRQ_NONE | PIIX2_CFG_PIRQ_MASK) << shift);
+ reg |= irq << shift;
+ pci_conf_write(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ1, reg);
+ }
+ }
+
+ return (0);
+}
+
+int
+piix2_get_trigger(v, irq, triggerp)
+ pciintr_icu_handle_t v;
+ int irq, *triggerp;
+{
+ struct piix2_handle *ph = v;
+ int off, bit;
+ u_int8_t elcr;
+
+ if (PIIX2_LEGAL_IRQ(irq) == 0)
+ return (1);
+
+ off = (irq > 7) ? 1 : 0;
+ bit = irq & 7;
+
+ elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
+ if (elcr & (1 << bit))
+ *triggerp = IST_LEVEL;
+ else
+ *triggerp = IST_EDGE;
+
+ return (0);
+}
+
+int
+piix2_set_trigger(v, irq, trigger)
+ pciintr_icu_handle_t v;
+ int irq, trigger;
+{
+ struct piix2_handle *ph = v;
+ int off, bit;
+ u_int8_t elcr;
+
+ if (PIIX2_LEGAL_IRQ(irq) == 0)
+ return (1);
+
+ off = (irq > 7) ? 1 : 0;
+ bit = irq & 7;
+
+ elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off);
+ if (trigger == IST_LEVEL)
+ elcr |= (1 << bit);
+ else
+ elcr &= ~(1 << bit);
+ bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr);
+
+ return (0);
+}
+
+#ifdef PIIX2_DEBUG
+void
+piix2_pir_dump(ph)
+ struct piix2_handle *ph;
+{
+ int i, irq;
+ pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ);
+ u_int8_t elcr[2];
+
+ elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0);
+ elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1);
+
+ for (i = 0; i < 4; i++) {
+ irq = PIIX2_PIRQ(irqs, i);
+ if (irq & PIIX2_CFG_PIRQ_NONE)
+ printf("PIIX2 PIRQ %d: irq none (0x%x)\n", i, irq);
+ else
+ printf("PIIX2 PIRQ %d: irq %d\n", i, irq);
+ }
+ irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX2_CFG_PIRQ1);
+ for (i = 8; i < 12; i++) {
+ irq = PIIX2_PIRQ(irqs, i);
+ if (irq & PIIX2_CFG_PIRQ_NONE)
+ printf("PIIX2 PIRQ %d: irq none (0x%x)\n", i, irq);
+ else
+ printf("PIIX2 PIRQ %d: irq %d\n", i, irq);
+ }
+ printf("PIIX2 irq:");
+ for (i = 0; i < 16; i++)
+ printf(" %2d", i);
+ printf("\n");
+ printf(" trigger:");
+ for (i = 0; i < 16; i++)
+ printf(" %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ?
+ 'L' : 'E');
+ printf("\n");
+}
+#endif /* PIIX2_DEBUG */
diff -ru --unidirectional-new-file /usr/src/sys/arch/i386/pci/piix2reg.h /u/NetBSD/lsrc/sys/arch/i386/pci/piix2reg.h
--- /usr/src/sys/arch/i386/pci/piix2reg.h 1970-01-01 01:00:00.000000000 +0100
+++ /u/NetBSD/lsrc/sys/arch/i386/pci/piix2reg.h 2002-08-21 17:33:23.000000000 +0200
@@ -0,0 +1,63 @@
+/* $NetBSD: piixreg.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1999, by UCHIYAMA Yasushi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the developer may NOT be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Register definitions for the Intel PIIX PCI-ISA bridge interrupt controller.
+ */
+
+/*
+ * PIRQ[3:0]# - PIRQ ROUTE CONTROL REGISTERS
+ *
+ * PCI Configuration registers 0x60, 0x61, 0x62, 0x63
+ *
+ * PIRQ[7:4]# - PIRQ ROUTE CONTROL REGISTERS
+ *
+ * PCI Configuration registers 0x68, 0x69, 0x6a, 0x6b
+ */
+
+
+#define PIIX2_LEGAL_LINK_60(link) ((link) >= 0 && (link) <= 3)
+#define PIIX2_LEGAL_LINK_68(link) ((link) >= 8 && (link) <= 0xb)
+#define PIIX2_LEGAL_LINK(link) (PIIX2_LEGAL_LINK_60(link) || PIIX2_LEGAL_LINK_68(link))
+
+#define PIIX2_PIRQ_MASK 0xdef8
+#define PIIX2_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
+ ((1 << (irq)) & PIIX2_PIRQ_MASK) != 0)
+
+#define PIIX2_CFG_PIRQ 0x60 /* PCI configuration space */
+#define PIIX2_CFG_PIRQ1 0x68 /* PCI configuration space */
+#define PIIX2_CFG_PIRQ_NONE 0x80
+#define PIIX2_CFG_PIRQ_MASK 0x0f
+#define PIIX2_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff)
+
+/*
+ * ELCR - EDGE/LEVEL CONTROL REGISTER
+ *
+ * PCI I/O registers 0x4d0, 0x4d1
+ */
+#define PIIX2_REG_ELCR 0x4d0
+#define PIIX2_REG_ELCR_SIZE 2
diff -ru --unidirectional-new-file /usr/src/sys/arch/i386/pci/piix2var.h /u/NetBSD/lsrc/sys/arch/i386/pci/piix2var.h
--- /usr/src/sys/arch/i386/pci/piix2var.h 1970-01-01 01:00:00.000000000 +0100
+++ /u/NetBSD/lsrc/sys/arch/i386/pci/piix2var.h 2002-08-20 13:32:49.000000000 +0200
@@ -0,0 +1,77 @@
+/* $NetBSD: piixvar.h,v 1.1 1999/11/17 01:21:21 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1999, by UCHIYAMA Yasushi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the developer may NOT be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Support for the Intel PIIX2 PCI-ISA bridge interrupt controller.
+ */
+
+int piix2_get_trigger __P((pciintr_icu_handle_t, int, int *));
+int piix2_set_trigger __P((pciintr_icu_handle_t, int, int));
+
+struct piix2_handle {
+ bus_space_tag_t ph_iot;
+ bus_space_handle_t ph_elcr_ioh;
+ pci_chipset_tag_t ph_pc;
+ pcitag_t ph_tag;
+};