[ On , October 22, 2002 at 17:15:27 (-0400), Nathan J. Williams wrote: ]
> Subject: Re: Offtopic, Mainboard recommandation
>
> With sufficently wide DIMMS, the chipset (AMD 760MPX) supports
> generating ECC data on write and checking ECC data on reads. If the
> right bit in the configuration is enabled, a fault is generated when
> an error (single or multibit) is detected. The fault is a PCI SERR#,
> which the southbridge can turn into a processor NMI).

Ah ha!  This is indeed more or less how I've come to understand many
such motherboards work.  What I'm less certain of is how many (or more
specifically exactly which models) have the NMI generation enabled by
default, and I'd like to learn how to check if it's enabled and how to
enable it if it's not already enabled by the BIOS.

> The BIOS for the board can enable ECC. I haven't yet glued code into
> NetBSD to enable the error reporting or the NMI.

Thank you very much for this information!

I'm guessing that NetBSS/i386 as yet has no generic support for ECC
reporting at all, is that right?

If I can do anything to help with getting this code in place and tested
on a wider variety of i386 machines then please do let me know!  In fact
I currently have an Elite Group Computer Systems P6FX1-A P-Pro
motherboard that occasionally triggers an NMI and I'm keen to diagnose
the cause of this and if it's due to ECC to know how often the corrected
error events happen.

I.e. while I appreciate the NMI for uncorrectable errors, I am just as
interested in receiving real-time notification from the kernel whenever
correctable errors are corrected, and hopefully in that notification is
some indication of what slot has the "failing" device.

-- 
								Greg A. Woods

+1 416 218-0098;            <g.a.woods@ieee.org>;           <woods@robohack.ca>
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