Has anyone seen/read any references to the interrupt latency
inherent in any of the recent Intel cpus?

I can't see any references in the standard Intel documents for the P2,
P3 or P4.

Note, I'm not interested in the OS latency, I want to know how
much of the interrupted code gets executed before the first instruction
of the interrupt handler.  In particular if an interrupt is pending
but the I flag is clear and you then set it, what value of the PC
will be stacked.

With the code below my athlon takes the pending interrupt after
the 'nop' (as expected).

	cli
	nop			# cli page says interrupt happens here...
	test	$1,memory	# look at data ISR would set.
	jnz	...

However a P2 takes it way, way later...

Is a serialiasation instruction going to help (ie wait for the ISR
to be entered) - such as:
	cli
	nop
	cpuid
	test	$1,memory

Actually cpuid is rather painful (trashes ax, bx, cx and dx) so the
alternative:
	cli
	nop
	movl	%dr0,%eax
	movl	%eax,%dr0
is rather more friendly.

	David

-- 
David Laight: david@l8s.co.uk