I have had no luck running this controller in DMA mode 5. I tried
changing the default in pciide.c to 5 with no luck, so it's clear I
don't understand the ide subsystem. According to the docs, this
controller supports UDMA 133 It appears that pciide.c and
pciide_apollo_reg.h need a change, but I don't know where to go
with this.

Could someone offer some guidance on what needs to be changed?

dmsg reports:

VIA Technologies VT82C586A IDE Controller (IDE mass storage, interface 0x8a, revision 0x06) at ? dev 17 function 1 (tag 0x80008900, intrtag 0x80008900, intrswiz
 0, intrpin 0x1, i/o on, mem on, no quirks): VIA Technologies unknown ATA controller
pciide0: bus-master DMA support present
pciide0: primary channel configured to compatibility mode
wd0 at pciide0 channel 0 drive 0: <WDC WD400BB-00CAA0>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 32253 MB, 4092 cyl, 16 head, 63 sec, 512 bytes/sect x 66055248 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
pciide0: primary channel interrupting at irq 14
wd0(pciide0:0:0): using PIO mode 4

(I had it wired to PIO mode in the kernel configuration on this boot.)

The output of pcictl follows.

Thanks.

-- jay

PCI configuration registers:
  Common header:
    0x00: 0x05711106 0x02900007 0x01018a06 0x00002000

    Vendor Name: VIA Technologies (0x1106)
    Device Name: VT82C586A IDE Controller (0x0571)
    Command register: 0x0007
      I/O space accesses: on
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
    Status register: 0x0290
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: mass storage (0x01)
    Subclass Name: IDE (0x01)
    Interface: 0x8a
    Revision ID: 0x06
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x20
    Cache Line Size: 0x00

  Type 0 ("normal" device) header:
    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
    0x20: 0x0000dc01 0x00000000 0x00000000 0x05711106
    0x30: 0x00000000 0x000000c0 0x00000000 0x000001ff

    Base address register at 0x10
      not implemented(?)
    Base address register at 0x14
      not implemented(?)
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      type: i/o
      base: 0x0000dc00, not sized
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x1106
    Subsystem ID: 0x0571
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0xc0
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0xff
    Capability register at 0xc0
      type: 0x01 (Power Management, rev. 1.0)

  Device-dependent header:
    0x40: 0x0509f20a 0x00c01c18 0x2000a8a8 0xb6b600ff
    0x50: 0x00000707 0x0000000c 0xa8a8a8a8 0x00000000
    0x60: 0x00000200 0x00000000 0x00000200 0x00000000
    0x70: 0x00000102 0x00000000 0x00000102 0x00000000
    0x80: 0x00080000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00020001 0x00000000 0x00000000 0x00000000
    0xd0: 0x05710006 0x05711106 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000