Well, inspired by PR11299, I've had a slightly closer look at the PCI BIOS
problems in my libretto. Essentially, it generates a uvm fault whilst
in the PCIBIOS "fetch interrupt table" code. It dies with:

    uvm_fault(0xc04826a0, 0x2000, 0, 1) -> e
    kerenel: page fault trap, code=0
    Stopped in pid 0 (swapper) at 0xc056ae8b: cmpb %cs:0x2db(%si),%al

At this point, %cs is 0x8, and %esi is 0xc0550000.

Unfortunately, I'm confused by all the different modes and segment
registers and god knows what in this stupid processor, so I'm wondering
just what location this is trying to access. Since I did a PCIBIOS call,
am I now in 16-bit mode at this point? Or do PCIBIOS calls happen in
32-bit mode? Is it really using just %si, and ignoring the upper half
of %esi, or is it using all of %esi? And, in the end, just what memory
location is it trying to access?

If someone were willing to help me out with this, I'd really appreciate
it. Unfortunately, I think the interrupt routing is going to be somewhat
screwed on my Libretto here until I can use the PCIBIOS to configure it.

cjs
-- 
Curt Sampson  <cjs@cynic.net>   +81 3 5778 0123   http://www.netbsd.org
    Don't you know, in this new Dark Age, we're all light.  --XTC