> Following up to the discussion regarding the support of the Promise
> Ultra/100 TX2 controller, I am trying to get the thing running but
> currently failing.

Following up once more, after a bit of poking around at least I now
have more details about the beast, having compiled a kernel with
DEBUG_PROBE in pciide.c

Device-specific output while booting now is:

| pciide1 at pci0 dev 11 function 0: Promise Ultra100/ATA Bus Master IDE Accelerator (rev. 0x01)
| PCI configuration registers:
|   Common header:
|     0x00: 0x4d68105a 0x04300007 0x01808501 0x00002008
|
|     Vendor Name: Promise Technology (0x105a)
|     Device Name: Ultra/100 ATA Bus Master IDE Accelerator (0x4d68)
|     Command register: 0x0007
|       I/O space accesses: on
|       Memory space accesses: on
|       Bus mastering: on
|       Special cycles: off
|       MWI transactions: off
|       Palette snooping: off
|       Parity error checking: off
|       Address/data stepping: off
|       System error (SERR): off
|       Fast back-to-back transactions: off
|     Status register: 0x0430
|       Capability List support: on
|       66 MHz capable: on
| User Definable Features (UDF) support: off
|       Fast back-to-back capable: off
|       Data parity error detected: off
|       DEVSEL timing: slow (0x2)
|       Slave signaled Target Abort: off
|       Master received Target Abort: off
|       Master received Master Abort: off
|       Asserted System Error (SERR): off
|       Parity error detected: off
|     Class Name: mass storage (0x01)
|     Subclass Name: miscellaneous (0x80)
|     Interface: 0x85
|     Revision ID: 0x01
|     BIST: 0x00
|     Header Type: 0x00 (0x00)
|     Latency Timer: 0x20
|     Cache Line Size: 0x08
|
|   Type 0 ("normal" device) header:
|     0x10: 0x0000d001 0x0000b801 0x0000b401 0x0000b001
|     0x20: 0x0000a801 0xe7000000 0x00000000 0x4d68105a
|     0x30: 0x00000000 0x00000060 0x00000000 0x1204010b
|
|     Base address register at 0x10
|       type: 32-bit i/o
|       base: 0x0000d000, size: 0x00000008
|     Base address register at 0x14
|       type: 32-bit i/o
|       base: 0x0000b800, size: 0x00000004
|     Base address register at 0x18
|       type: 32-bit i/o
|       base: 0x0000b400, size: 0x00000008
|     Base address register at 0x1c
|       type: 32-bit i/o
|       base: 0x0000b000, size: 0x00000004
|     Base address register at 0x20
|       type: 32-bit i/o
|       base: 0x0000a800, size: 0x00000010
|     Base address register at 0x24
|       type: 32-bit nonprefetchable memory
|       base: 0xe7000000, size: 0x00004000
|     Cardbus CIS Pointer: 0x00000000
|     Subsystem vendor ID: 0x105a
|     Subsystem ID: 0x4d68
|     Expansion ROM Base Address: 0x00000000
|     Capability list pointer: 0x60
|     Reserved @ 0x38: 0x00000000
|     Maximum Latency: 0x12
|     Minimum Grant: 0x04
|     Interrupt pin: 0x01 (pin A)
|     Interrupt line: 0x0b
|     Capability register at 0x60
|       type: 0x01 (Power Management, rev. 1.0)
|
|   Device-dependent header:
|     0x40: 0x00000000 0x00000000 0x00000000 0x00000000
|     0x50: 0x00000000 0x00000000 0x00000000 0x00000000
|     0x60: 0x02010001 0x00000000 0x00000000 0x00000000
|     0x70: 0x00000000 0x00000000 0x00000000 0x00000000
|     0x80: 0x00000000 0x00000000 0x00000000 0x00000000
|     0x90: 0x00000000 0x00000000 0x00000000 0x00000000
|     0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
|     0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
|     0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
|     0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
|     0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
|     0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
|
|     Don't know how to pretty-print device-dependent header.
|
| pdc202xx_setup_chip: controller state 0x0
| pciide1: bus-master DMA support present
| pdc202xx_setup_chip: channel 0 drive 0 initial timings  0x2010001, now 0x457309
| pdc202xx_setup_chip: channel 0 drive 1 initial timings  0x0, now 0x57309
| pdc202xx_setup_chip: channel 1 drive 0 initial timings  0x0, now 0x457309
| pdc202xx_setup_chip: channel 1 drive 1 initial timings  0x0, now 0x57309
| pdc202xx_setup_chip: initial SCR  0xffffffff, now 0x1130001
| pdc202xx_setup_chip: primary mode 0xff, secondary mode 0xff
| pciide1: primary channel configured to compatibility mode
| pciide1: primary channel ignored (disabled)
| pciide1: secondary channel configured to compatibility mode
| pciide1: secondary channel ignored (disabled)
| pdc202xx_setup_chip: new controller state 0x0
| pciide: command/status register=4300007
| isa0 at pcib0

What I probably forgot to mention the last time 'round is that I'm
running the 1.5T snapshot.

Hoping that this is at least partially helpful,
 Konrad

===8<===========End of original message text===========



-- 
Best regards,
 Konrad                            mailto:konrad@fimsch.net