> Does anonyone know when Intel P3 SIMD instructions will be supported
> in NetBSD? Or more specifically, the saving of the "fpu" state 
> in "npx.c" (there are now an additional 8 128-bit registers).  

This is something of a chicken and egg problem... if there's no code
out there which wants to use the SSE extensions, the folks writing the
kernel code don't have any reason to implement the context switch code
needed for it when everyone's breathing down their neck for other
features like kernel threads and multiprocessor support ;-)

Anyhow, if anyone wants to implement this..  I looked at this briefly
when I was working on the MP lazy fp save/restore as part of the i386
MP work -- the P3 introduced a new allegedly faster floating-point/mmx
context save/restore instruction pair, the presence of which is
identified by a different CPU feature bit from the SSE goo... and that
instruction is implemented on at least some celeron CPU's as well...

						- Bill