On Thu, Oct 05, 2000 at 04:41:53PM -0700, Jason R Thorpe wrote:
> So, I just heard for the first time today that some people hare having
> K6 issues wrt. zero page idling -- wasn't aware of that.  So, this goes
> back to the problems we saw with the Cyrix CPUs.  I think the way the
> pmap is doing TLB invalidation is a little sketchy.

I don't think it's causing any problems on K6 CPUs.. one vague report
I saw was more likely due to bad memory.

> 
> I've attached a diff that I'd like people with Cyrix CPUs to try.  It's
> relative to the 1.5 branch.  Please see if this works in the presence
> of idle page zero'ing.

Page zeroing is switched off for Cyrix processors, and this diff won't
change that. However, at least one person has been reporting that
switching off page zeroing did not actually help on his Cyrix (although
it did for others). I sent him a patch similar to what you did, and
it seems to have had a beneficial effect.

It would be interesting to see what happens for people with Cyrix CPUs
that re-enable page zeroing, and include your patch.

To re-enable page zeroing, please apply the diff below to
sys/arch/i386/i386/machdep.c

- Frank


Index: machdep.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/i386/i386/machdep.c,v
retrieving revision 1.389.2.2
diff -c -r1.389.2.2 machdep.c
*** machdep.c	2000/08/17 18:52:55	1.389.2.2
--- machdep.c	2000/10/06 12:07:04
***************
*** 669,675 ****
  	 * XXX disable page zero in the idle loop, it seems to
  	 * cause panics on these CPUs.
  	 */
! 	vm_page_zero_enable = FALSE;
  }
  
  void
--- 669,675 ----
  	 * XXX disable page zero in the idle loop, it seems to
  	 * cause panics on these CPUs.
  	 */
! 	vm_page_zero_enable = TRUE;
  }
  
  void