Currently the interrupt despatching mechanism in NetBSD/i386 is very
dependent on the i8259 interrupt controller.  It would be great to
remove this dependence, particularly in the case of symmetric I/O (SMP).

An MI interrupt despatching mechanism which interfaced to ICU-dependent
drivers looks like the way to go.  This approach doesn't look like
a big issue, except perhaps an increased latency.

What is confusing, is how to handle spl levels.  How many IRQs can be
expected to be supported this way?

Does anyone have any comments/ideas on the subject?

	-- Gregory McGarry <g.mcgarry@qut.edu.au>