Subject: Re: PCIC interrupt selection
To: None <rvb@sicily.odyssey.cs.cmu.edu>
From: Perry E. Metzger <perry@piermont.com>
List: port-i386
Date: 08/10/1998 17:13:49
rvb@sicily.odyssey.cs.cmu.edu writes:
> But not only do we need to set allowable irq's but also 
> allowable ports.  The 560X enables a parallel port at 0x3bc,
> which makes the next allocation request (for ether in my case)
> get 0x3cc.  This is where the neomagic chip lives -- TILT!

Sigh.

.pm