Subject: New IDE system: first pass
To: None <current-users@NetBSD.ORG, port-i386@NetBSD.ORG>
From: Manuel Bouyer <email@example.com>
Date: 05/20/1998 13:36:30
I've made a preliminary release of the new ide system I'm working on
available. It's in ftp://ftp.netbsd.org:/pub/incoming/bouyer/newide.tar.gz
This file has to be extracted in /usr/src/sys. It contains a buch of
new files, and a patch file (apply with 'patch -p < ide.diff').
The core ide driver now contains 3 files: dev/ic/wdc.c, dev/ata/ata_wdc.c
and dev/scsipi/atapi_wdc.c, containing respectively the common, ata-specific
and atapi-specific functions. For the benefit of pciide, this core driver has
now another attribute: channel, so a device is now identified by 'ctrl,
channel #, drive #'. This also means that wd and atapibus attach directly
to pciide. (Look at the GENERIC config file, it has all the needed changes).
dev/ic/wdc.c implements a machinery to send simple commands to a device
(eventually with data read/writes). It can poll for completion, wait for
completion using interrupts/tsleep or call a user-provided callback when
dev/ata/ata_wdc.c implements the machinery for READ/WRITES (for now
only PIO_SINGLE and PIO_MULTI) in both interrupts and polled mode.
dev/scsipi/atapi_wdc.c implements the machinery for packets commands,
in both interrupts and polled mode.
These 3 machineries use a common queue.
32-bit PIO access are supported, they have to be enabled in the kernel config
file via flags (look at comments in GENERIC about this). I'll look at adding
autodetection for this later.
I added a table of supported devices vendor/IDs to pciide.c. It is used at
probe/attach time, the device has to be in the table to be attached.
The reason for this is that I found some devices don't behave in a standart
way, preventing the machine to boot. Claiming support for any PCI IDE chip
may end up in loosages for users. On PCs, unknown PCI IDE chips will
still attach via the standart ISA driver.
The 'brocken' CMD PCI0640 pci ide controller should now be fully supported
by PCIIDE, but I've tested it with only one drive yet.
This code has been tested with various controllers (only isa and pci
fron-ends). Unfortunably I don't have really old drives to play with, so I
don't know if I've broken something for theses or not. If someone with an
hardware museum could try it out ...
I will now start working on IDE DMA (and possibly ultra/33), power management
and other features.
Manuel Bouyer, LIP6, Universite Paris VI. Manuel.Bouyer@lip6.fr