Subject: Re: README: Changes to PCI, ISA
To: None <email@example.com>
From: Chris G Demetriou <Chris_G_Demetriou@auchentoshan.pdl.cs.cmu.edu>
Date: 11/28/1996 01:53:43
[ jonathan: your mailer set a reply-to of:
Reply-To: Jason Thorpe <firstname.lastname@example.org>
... _That_ is a bug report. 8-]
> This is not a bug report. It's a philosophical question.
> Shouldn't the pci host-brige chipset be on the mainbus,
> with the pci bus attached to *it*, rather than vice-versa?
Yes and no. For instance, the alpha does it the way you say it should
Indeed, the i386 _could_ do it that way, too, but:
> Why is the config done the way it is? Perhaps because the
> PCI host brige is discovered by probing PCI configuration space?
The host bridge will show up in PCI-space no matter what, on x86en
that have host bridges that ever show up in PCI space.
Therefore, on those x86en, you'd end up with something like:
mainbus0 at root
pcifrob0 at mainbus0
pci0 at pcifrob0 ...
pchb0 at pci0 ...
That's sort of nasty.
In reality, it may actually make sense to do something like that,
pre-probing the PCI bus via MD code. The problem is to work around
some chipset bugs, what you really want to do is pass down to all
drivers certain values (e.g. the max burst size they should enable).
If you do the attachment the way it's currently done, you can't do
that. (how do you go back and update the devices that you've already
seen before you come to the pchb? Even if you can do that, how do you
set the values appropriately in the _parent_ pci bus?)
There was a reason why i hadn't filed lack of i386 PCI host bus bridge
support as a bug; it's not quite _so_ straightforward to do