Subject: Re: README: Changes to PCI, ISA
To: Jason Thorpe <>
From: Jonathan Stone <jonathan@DSG.Stanford.EDU>
List: port-i386
Date: 11/27/1996 22:43:10
>NetBSD 1.2B (DRACUL) #26: Thu Nov 28 11:40:18 PST 1996
>    thorpej@dracul:/sys/arch/i386/compile/DRACUL
>CPU: Pentium Pro (GenuineIntel 686-class CPU)
>real mem  = 66711552
>avail mem = 60874752
>using 839 buffers containing 3436544 bytes of memory
>mainbus0 (root)
>pci0 at mainbus0 bus 0: configuration mode 1
>pchb0 at pci0 dev 0 function 0
>pchb0: Intel 82440FX (Natoma) PCI and Memory Controller (rev. 0x02)
>pcib0 at pci0 dev 1 function 0
>pcib0: Intel 82371SB (Triton II) PCI-ISA Bridge (rev. 0x01)

Yikes, wow, neat, thanks for  doing this!

>If you have any questions or problems with the new code, please let
>me know (by filing a bug report with send-pr(1) :-).

This is not a bug report.  It's a philosophical question.
Shouldn't the pci host-brige chipset be on the mainbus,
with the pci bus attached to *it*, rather than vice-versa?

You have  a hierarcy that looks, in part, like this
(rearranging vertical things to make the ancestry clearer)

        pci host bridge chipset
            [other PCI devices]
            pci-ISA bridge chipset
	        isa bus
                    [isa devices]

There's an asymmetry there. It looks to me like the host-pci
bridge  and the pci bus should be exchanged, i.e.,

    pci host bridge chipset
            [other PCI devices]
            pci-ISA bridge chipset
	        isa bus
                    [isa devices]

is more consistent with how other things (scsi busses, the PCI-ISA
host bridge,  PCMCIA?)   are/will work.

Why is the config done the way it is? Perhaps because the
PCI host brige is discovered by probing PCI configuration space?
Could the reason be explained, perhaps in a man page?
(if they are, sorry, I'm waiting for sup :))