Subject: Re: Physical memory tests?
To: None <port-i386@NetBSD.ORG>
From: Terry Moore <firstname.lastname@example.org>
Date: 08/03/1996 21:11:56
> Are you sure? I was under the impression that it required one or two
> extra bits. But, I'm no expert on the subject... I just know ECC
> SIMMs are a lot more expensive than "normal" SIMMs.
ECC bits required scale as lg2(wordsize protected); for 64
bits you need 8 extra; ditto for byte parity. Note, though, that
if you are ECCing 64-bit words there are two practical problems:
1) 32-bit writes require r/m/w cycles, which slows things down a lot.
2) It is not completely clear that ability to correct any single-bit
error (in a 64-bit word) and detect any two-bit error give a longer
MTBF when compared to per-byte parity. Consider: any error that
would be corrected by ECC would be detected by parity. Since the
described situation was undetected errors, and multi-bit errors tend
to come in multiples greater than 2 (they're usually due to connector faults
or broken multi-bit silicon; common widths are x1 and x4), it is not
even clear that ECC would have helped in this situation. Admittedly,
a carefully designed ECC system can still catch the "common" failure