"Justin T. Gibbs" <gibbs@freefall.freebsd.org> writes:

> 
> >(There appears to be a design flaw in the chip that precludes the use
> >of synchronous mode with PIO.  This causes the driver to lose with
> >some fast devices, until a few minutes ago when I disabled synchronous
> >mode in -current.  I've analyzed this problem fairly thoroughly, and
> >sent off a few queries to Adaptec, but have received no answers at
> >all.)
> 
> Does the 6360 have a CLRCHN control bit?  If so, when are you setting
> it?  This sounds very similar to an ancient bug in the aic7xxx
> sequencer code (two years ago by now?).  CLRCHN must be set immediately
> after the (re)selection in order to not lose data on fast devices in
> sync mode.

No; this is a very different problem.  Basically, if you've set
synchronous mode, the chip will happily start receiving data off the
SCSI bus into the FIFO once the target has switched from COMMAND phase
to DATA IN phase, before you've changed SCSISIG.  As far as I can
tell, this makes it impossible to determine whether or not the whole
command actually made it out.  The same thing happens when switching
from DATA OUT phase to DATA IN phase.

The only driver I could find that actually uses synchronous mode is
Adaptec's own, and it appears to not deal with this.