port-hpcmips: Re: Vr4131 cache configuration

Subject: Re: Vr4131 cache configuration
To: Warner Losh <imp@harmony.village.org>
From: TAKEMURA Shin <takemura@netbsd.org>
List: port-hpcmips
Date: 12/23/2001 22:09:23

----- Original Message ----- 
From: "Warner Losh" <imp@harmony.village.org>
To: "TAKEMURA Shin" <takemura@netbsd.org>
Cc: <port-mips@netbsd.org>; <port-hpcmips@netbsd.org>
Sent: Monday, December 17, 2001 12:02 PM
Subject: Re: Vr4131 cache configuration 


> In message <04f401c1863f$a079c100$cb01a8c0@megu2> "TAKEMURA Shin" writes:
> : +               if (!(MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 &&
> : +                   (MIPS_PRID_REV(cpu_id) & 0x80))) {
> 
> Does NEC say that all the Vr41xx processors with a PRID_REV of 0x80
> will have this kind of cache?

No! :-(

Takemura