Subject: Re: Vr4131 cache configuration
To: TAKEMURA Shin <takemura@netbsd.org>
From: Warner Losh <imp@harmony.village.org>
List: port-hpcmips
Date: 12/16/2001 20:02:57 
In message <04f401c1863f$a079c100$cb01a8c0@megu2> "TAKEMURA Shin" writes:
: +               if (!(MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 &&
: +                   (MIPS_PRID_REV(cpu_id) & 0x80))) {

Does NEC say that all the Vr41xx processors with a PRID_REV of 0x80
will have this kind of cache?

Warner