Hi,

I added macros to operate SA1110 LCD resisters to sa11x0_lcdreg.h.
Please use it as you like.

I have JORNADA710 (It is same JORNADA720 mostly). I want to use its LCD
display and I am testing to set various values to LCD resisters of SA1110.
But, the LCD display doesn't work correctly...



--- sa11x0_lcdreg.h.orig	Fri May 25 01:10:50 2001
+++ sa11x0_lcdreg.h	Tue May  1 02:45:16 2001
@@ -45,6 +45,11 @@
 #define SALCD_12_16_OFFSET	0x20	/* 12BIT - 16BIT */
 #define SALCD_8BIT_OFFSET	0x200	/*  8BIT */
 
+/* LCD framebuffer pixel bit size */
+#define SALCD_4_PBS		(0<<12) /* 4bit/pixel, 16 palette */
+#define SALCD_8_PBS		(1<<12) /* 8bit/pixel, 256 palette */
+#define SALCD_12_16_PBS		(2<<12) /* 12-16bit/pixel, no palette */
+
 /* LCD Control Register 0 */
 #define SALCD_CR0	0
 #define CR0_LEN		(1<<0)	/* LCD enable */
@@ -56,30 +61,32 @@
 #define CR0_ERM		(1<<5)	/* Bus error generate an intrrupt */
 #define CR0_PAS		(1<<7)	/* Passive / Active and TFT-LCD enable */
 #define CR0_BLE		(1<<8)	/* endial select 0=little */
-#define CR0_DPD		(1<<9)
+#define CR0_DPD		(1<<9)  /* double pixel mode */
+#define CR0_PDD(x)	(((x) &  0xff) << 12) /* pallete DMA request delay */
 
 /* LCD Control Register 1 */
 #define SALCD_CR1	0x20
-	/* PPL ; Pixel per line - 16 */
-	/* HSW ; */
-	/* ELW ; */
-	/* BLW ; */
+#define CR1_PPL(x)	(((x)&0x3ff)<< 0) /* pixel per line - 16 */
+#define CR1_HSW(x)	(((x)& 0x3f)<<10) /* horizontal sync pulse width - 1 */
+#define CR1_ELW(x)	(((x)& 0xff)<<16) /* End-of-line pixel clock wait count - 1 */
+#define CR1_BLW(x)	(((x)& 0xff)<<24) /* Begin-of-line pixel clock wait count - 1 */
 
 /* LCD Control Register 2 */
 #define SALCD_CR2	0x24
-	/* LPP ; Lines per panel */
-	/* VSW ; */
-	/* EFW ; */
-	/* BFW ; */
+#define CR2_LPP(x)	(((x)&0x3ff)<< 0) /* lines per panel - 1*/
+#define CR2_VSW(x)	(((x)& 0x3f)<<10) /* vertical sync pulse width - 1 */
+#define CR2_EFW(x)	(((x)& 0xff)<<16) /* End-of-frame line clock wait count */
+#define CR2_BFW(x)	(((x)& 0xff)<<24) /* Beginning-of-frame line clock wait count */
 
 /* LCD Control Register 3 */
 #define SALCD_CR3	0x28
-	/* PCD ; Pixel clock divisor	*/
-	/* ACB ; */
-	/* API ; AC Bias 		*/
-	/* VSP ; Vertical sync		*/
-	/* HSP ; Horizontal sync	*/
-	/* PCP ; Pixel clock polarity	*/
+#define CR3_PCD(x)	(((x)&0xff)<< 0) /* pixel clock divider */
+#define CR3_ACB(x)	(((x)&0xff)<< 8) /* AC bias pin frequency - 1*/
+#define CR3_API(x)	(((x)& 0xf)<<16) /* AC bias pin transitions per interrupt */
+#define CR3_VSP		(1<<20) /* vertical sync polarity */
+#define CR3_HSP		(1<<21) /* horizontal sync polarity */
+#define CR3_PCP		(1<<22) /* pixel clock polarity */
+#define CR3_OEP		(1<<23) /* output enable polarity */
 
 /* DMA Channel 1 Base Address Register */
 #define SALCD_BA1	0x10