Subject: Re: Utility chip sio's on 4xx (more stories)
To: Michael Smith <firstname.lastname@example.org>
From: Michael Joosten <email@example.com>
Date: 03/21/1997 04:22:34
>Dunno about that; I'm just really annoyed that something like this has
>slipped for so long (heck, even the HPBSD didn't support this chip!).
Me too, 'cuz I just have Domain/OS keyboard, like you...
>The 8250 is the original part in the family. The 16450 is basically
>the same, but a little faster and more reliable at high speeds. The
OK, I did not know how the 8250 fitted in the picture.
>An 8-byte _output_ fifo? Obviously designed for terminals or printers?
Sounds weird, but I vaguley remeber having read a similar thing in the
datasheet of an 2681. But don't nail me down...
I'm experimenting with Domain/OS monitor in service mode (button and green
LED), which has a simple machine code monitor build in. I was just too lazy to
figure out how to use kgdb or such...
So, actually, I don't have *any* documentation about the hardware at all, not
even the blurb that should accompany the box. It was exchanged from some other
department ages ago... What I know is either rengineered or deduced from some
Apollo release notes and such. Sorry, no more miraculous docs in my hat...
>I wonder if the PIO has something to do with the parallel port; I
>pulled the driver for it apart but the base address appears to be
I don't think so: there is a different HP parallel device announcing itself
during startup at some 'resonable' scode ( and that's probably the reason why
the code gets the base addr. passed in from system config):
BOOTROM Series 400 Rev. 1.1
MD12 REV 1.2 1990/08/07.14:27:08
HP98644 (RS-232) at 9
HP PARALLEL at 12
HP98265 (SCSI S 32) at 14
and there is some address space mapped at 0x600000 + 9 * 0x10000:
>D 690000 690100
690000: FFC2 FF20 FFC2 FF20 FFC2 FF20 FFC2 FF20
690010: FF80 FF00 FF01 FF07 FF00 FF60 FF0F FFFF
690020: FFC2 FF20 FFC2 FF20 FFC2 FF20 FFC2 FF20
690030: FF80 FF00 FF01 FF07 FF00 FF60 FF00 FFFF
.. but I'm a bit surprised why that parallel port takes almost 16 registers, as
the values of ...10 - ...1f are not repeating or mirrored. (..00- ..0f is the
usual HP card identifier and such) I got the apollo_pci.o just from HP patch
archive, I'm not sure if there is also a patch containing the module for the
The extended selftest confirms some of my guesses:
UTILITY CHIP SIO TESTS STARTED
Internal Loopback SIO 0 - PASSED
Internal Loopback SIO 1 - PASSED
Internal Loopback SIO 2 line in use - SKIPPED
Internal Loopback SIO 3 - PASSED
UTILITY CHIP SIO TESTS COMPLETED
SIO LOOPBACK TESTS STARTED
SIO Loopback Device - ABSENT
SIO LOOPBACK TESTS COMPLETED
DOMAIN KEYBOARD TESTS STARTED
Keyboard Tests - PASSED
DOMAIN KEYBOARD TESTS COMPLETED
UTILITY CHIP INTERRUPT TESTS STARTED
Interrupt I/O Tests - PASSED
Priority Interrupt Tests - PASSED
Timer Overflow Register Increment - PASSED
UTILITY CHIP INTERRUPT TESTS COMPLETED
>They didn't bother emulating the 2681, why go with the 6840? More
>interestingly, perhaps, can the timer generate interrupts?
I'd guess they had to provide a timer with Domain/OS suitable function, as the
comments in NetBSD indicate that the HP one is already 'wired': two counter are
concatenated. And perhaps the clock is different. Interrupts... generally an
interesting question, also for the sio ports... but a timer without interrupts
doesn't make much sense in a multitasking os, does it? Perhaps the 'fake' scode
of the utility chip (41) or the blurb of changing the scode in the driver and
also in the configuration part of the monitor PROM gives a hint on what
interrupt level it can work. (Priority Interrupt Tests, UTIL_PIC, perhaps means
Priority Interrupt Controller, hmmm...)
>Finding the ISA slot would be a winner too (anything in the apollo info
>that you have there?)
Sorry, no docs at all. Someone (Herb Peyerl?) told me ages ago that mixing the
ISA bus stuff in the kernel will make things quite messy...
>> clock frequency...
Well, there is an 14.318 Mhz oscillator near the 16550 on the board (together
with a 40 Mhz one), but it does not seem to be directly connected to the 16550.
But I'd assume that, since both port types are so similar, they use the same
master clock - I hope... At least for the domain side, the divisors seem to be
correct for the domain keyb, as I can properly read keys out of the register.
Or is it possible to read these divisor latches back ? No, doesn't seem to
How did you create the dissasembly? Looks quite nice...where did you get the
reloc info from?
So far. Michael