garrett_damore@tadpole.com wrote:

> Attached is the following patch, which borrows code from
> mips/mips/mips3_clock.c, to use a cp0 based timecounter  for ews4800mips.

Looks good, but I'll test it tomorrow. (I have to go to bed soon...)

> I have _not_ converted the clock code to just use
> mips/mips/mips3_clock.c directly.  I think that would be a good idea,
> but I saw some possible issue with cpu_initclocks(), and enabling the
> PICNIC interrupt.
> 
> Someone else can do that cleanup.  (And I highly recommend it be done.)

Currently we could not, because on these ews4800mips machines
CPU INT5 is connected to external interval timers
(not CPU internal compare register), and PICNIC or INTC
enables/disables the interrupt line.
(see a figure in sys/arch/ews4800mips/include/sbd_tr2a.h)

i.e. ews4800mips uses the MIPS3 internal counter only for delay()
and microtime(), and no mips3_cp0_compare_write() in arch/ews4800mips.
(maybe some more ifdefs are required in mips3_clock.c...)
---
Izumi Tsutsui