Subject: Re: How to implement PSC driver on Au1550
To: Shigeyuki Fukushima <shige@NetBSD.org>
From: Garrett D'Amore <garrett_damore@tadpole.com>
List: port-evbmips
Date: 02/23/2006 12:56:28
Shigeyuki Fukushima wrote:
> Garrett D'Amore wrote:
>
>> Looks reasonable. I don't have any objections if you want to commit
>> this, as it isn't in any default configs yet. (C.F. my PCMCIA commits.)
>>
>
> I re-wrote an aupsc driver.
> We need to implement selecting protocol and locking bus features.
> Would you like to review it?
>
This looks good. One obvious point, you misspelled "unable" in the
error message below. (search for "unbale"). :-) Also there was an
indent error in aupsc_attach (see the line that starts bus_space_write.)
What exactly are you planning on locking, though? It looks to me like
the registers for each PSC are independent from each other, so you
shouldn't need to lock them.
Additionally, I'm not sure whether there is much point in adding locks
as opposed to using splhigh() to protect register accesses. The Alchemy
platform is, and will probably always be, strictly a uniprocessor
platform, so alchemy specific code probably doesn't need to deal with
fine grained locks.
Of course, architecturally, fine grained locking is cleaner, and if we
are going to be making a general push in that direction for all
platforms, then by all means go ahead and use them. :-) (I'll defer to
the wisdom of the greater NetBSD community here. :-)
Hmm... I'm also not sure about the clock selection logic in general.
How do you know which clock to select? That seems to be a board
specific configuration option. Maybe another set of board_info() ops?
Or another locator? I don't know what the right option is. (In any
case, it seems likely that you need expose some aupsc operations to
individual drivers -- e.g. aupsc_enable()/disable()/suspend(),
aupsc_set_protocol(), aupsc_set_clock() maybe?
-- Garrett
>
> ------------------------------------------------------------------------
>
> /* $NetBSD$ */
>
> /*-
> * Copyright (c) 2006 Shigeyuki Fukushima.
> * All rights reserved.
> *
> * Written by Shigeyuki Fukushima.
> *
> * Redistribution and use in source and binary forms, with or without
> * modification, are permitted provided that the following conditions
> * are met:
> * 1. Redistributions of source code must retain the above copyright
> * notice, this list of conditions and the following disclaimer.
> * 2. Redistributions in binary form must reproduce the above
> * copyright notice, this list of conditions and the following
> * disclaimer in the documentation and/or other materials provided
> * with the distribution.
> * 3. The name of the author may not be used to endorse or promote
> * products derived from this software without specific prior
> * written permission.
> *
> * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
> * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
> * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
> * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
> * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
>
> #include <sys/cdefs.h>
> __KERNEL_RCSID(0, "$NetBSD$");
>
> #include "locators.h"
>
> #include <sys/param.h>
> #include <sys/systm.h>
> #include <sys/device.h>
> #include <sys/errno.h>
> #include <sys/lock.h>
>
> #include <machine/bus.h>
> #include <machine/cpu.h>
>
> #include <mips/alchemy/include/aubusvar.h>
> #include <mips/alchemy/include/aureg.h>
> #include <mips/alchemy/dev/aupscreg.h>
> #include <mips/alchemy/dev/aupscvar.h>
>
> struct aupsc_softc {
> struct device sc_dev;
> bus_space_tag_t sc_bust;
> bus_space_handle_t sc_bush;
> int sc_pscsel;
> struct lock sc_buslock;
> };
>
> const struct aupsc_proto {
> const char *name;
> } aupsc_protos [] = {
> #if 0
> { "auaudio" },
> { "aui2s" },
> { "ausmbus" },
> { "auspi" },
> #endif
> { NULL }
> };
>
> static int aupsc_match(struct device *, struct cfdata *, void *);
> static void aupsc_attach(struct device *, struct device *, void *);
> static int aupsc_submatch(struct device *parent, struct cfdata *cf,
> const int *ldesc, void *aux);
> static int aupsc_print(void *aux, const char *pnp);
>
> CFATTACH_DECL(aupsc, sizeof(struct aupsc_softc),
> aupsc_match, aupsc_attach, NULL, NULL);
>
> static int
> aupsc_match(struct device *parent, struct cfdata *cf, void *aux)
> {
> struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
>
> if (strcmp(aa->aa_name, cf->cf_name) != 0)
> return 0;
>
> return 1;
> }
>
> static void
> aupsc_attach(struct device *parent, struct device *self, void *aux)
> {
> int i;
> u_int32_t rv;
> struct aupsc_softc *sc = (struct aupsc_softc *)self;
> struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
> struct aupsc_attach_args pa;
>
> sc->sc_bust = aa->aa_st;
> if (bus_space_map(sc->sc_bust, aa->aa_addr,
> AUPSC_SIZE, 0, &sc->sc_bush) != 0) {
> aprint_normal(": unbale to map device registers\n");
> return;
> }
>
> lockinit(&sc->sc_buslock, PRIBIO|PCATCH, "aupsclk", 0, 0);
>
> /* Initialize PSC_SEL register */
> sc->sc_pscsel = AUPSC_SEL_DISABLE;
> rv = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPSC_SEL);
> bus_space_write_4(sc->sc_bust, sc->sc_bush,
> AUPSC_SEL, (rv & AUPSC_SEL_PS(AUPSC_SEL_DISABLE)));
>
> aprint_normal(": Alchemy PSC\n");
>
>
> for (i = 0 ; aupsc_protos[i].name != NULL ; i++) {
> pa.aupsc_name = aupsc_protos[i].name;
> pa.aupsc_bust = sc->sc_bust;
> pa.aupsc_bush = sc->sc_bush;
> pa.aupsc_buslock = &(sc->sc_buslock);
>
> (void) config_found_sm_loc(self, "aupsc", NULL,
> &pa, aupsc_print, aupsc_submatch);
> }
> }
>
> static int
> aupsc_submatch(struct device *parent, struct cfdata *cf,
> const int *ldesc, void *aux)
> {
>
> return (config_match(parent, cf, aux));
> }
>
> static int
> aupsc_print(void *aux, const char *pnp)
> {
> struct aupsc_attach_args *pa = aux;
>
> if (pnp)
> aprint_normal("%s at %s", pa->aupsc_name, pnp);
>
> return (UNCONF);
> }
>
> ------------------------------------------------------------------------
>
> /* $NetBSD$ */
>
> /*-
> * Copyright (c) 2006 Shigeyuki Fukushima.
> * All rights reserved.
> *
> * Written by Shigeyuki Fukushima.
> *
> * Redistribution and use in source and binary forms, with or without
> * modification, are permitted provided that the following conditions
> * are met:
> * 1. Redistributions of source code must retain the above copyright
> * notice, this list of conditions and the following disclaimer.
> * 2. Redistributions in binary form must reproduce the above
> * copyright notice, this list of conditions and the following
> * disclaimer in the documentation and/or other materials provided
> * with the distribution.
> * 3. The name of the author may not be used to endorse or promote
> * products derived from this software without specific prior
> * written permission.
> *
> * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
> * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
> * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
> * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
> * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
>
> #ifndef _MIPS_ALCHEMY_DEV_AUPSCREG_H_
> #define _MIPS_ALCHEMY_DEV_AUPSCREG_H_
>
> /*
> * PSC registers (offset from PSCn_BASE).
> */
>
> /* psc_sel: PSC clock and protocol select
> * CLK [5:4]
> * 00 = pscn_intclk (for SPI, SMBus, I2S Master[PSC3 Only])
> * 01 = PSCn_EXTCLK (for SPI, SMBus, I2S Master)
> * 10 = PSCn_CLK (for AC97, I2S Slave)
> * 11 = Reserved
> * PS [2:0]
> * 000 = Protocol disable
> * 001 = Reserved
> * 010 = SPI mode
> * 011 = I2S mode
> * 100 = AC97 mode
> * 101 = SMBus mode
> * 11x = Reserved
> */
> #define AUPSC_SEL 0x00 /* R/W */
> # define AUPSC_SEL_CLK(x) ((x & 0x03) << 4) /* CLK */
> # define AUPSC_SEL_PS(x) (x & 0x07)
> # define AUPSC_SEL_DISABLE 0
> # define AUPSC_SEL_SPI 2
> # define AUPSC_SEL_I2S 3
> # define AUPSC_SEL_AC97 4
> # define AUPSC_SEL_SMBUS 5
>
> /* psc_ctrl: PSC control
> * ENA [1:0]
> * 00 = Disable/Reset
> * 01 = Reserved
> * 10 = Suspend
> * 10 = Enable
> */
> #define AUPSC_CTRL 0x04 /* R/W */
> # define AUPSC_CTRL_ENA(x) (x & 0x03)
>
> /* 0x0008 - 0x002F: Protocol-specific registers */
>
> /* PSC registers size */
> #define AUPSC_SIZE 0x2f
>
>
> /*
> * SPI Protocol registers
> */
> #define AUPSC_SPICFG 0x08 /* R/W */
> #define AUPSC_SPIMSK 0x0c /* R/W */
> #define AUPSC_SPIPCR 0x10 /* R/W */
> #define AUPSC_SPISTAT 0x14 /* Read only */
> #define AUPSC_SPIEVNT 0x18 /* R/W */
> #define AUPSC_SPITXRX 0x1c /* R/W */
>
> /*
> * I2S Protocol registers
> */
> #define AUPSC_I2SCFG 0x08 /* R/W */
> #define AUPSC_I2SMSK 0x0c /* R/W */
> #define AUPSC_I2SPCR 0x10 /* R/W */
> #define AUPSC_I2SSTAT 0x14 /* Read only */
> #define AUPSC_I2SEVNT 0x18 /* R/W */
> #define AUPSC_I2STXRX 0x1c /* R/W */
> #define AUPSC_I2SUDF 0x20 /* R/W */
>
> /*
> * AC97 Protocol registers
> */
> #define AUPSC_AC97CFG 0x08 /* R/W */
> #define AUPSC_AC97MSK 0x0c /* R/W */
> #define AUPSC_AC97PCR 0x10 /* R/W */
> #define AUPSC_AC97STAT 0x14 /* Read only */
> #define AUPSC_AC97EVNT 0x18 /* R/W */
> #define AUPSC_AC97TXRX 0x1c /* R/W */
> #define AUPSC_AC97CDC 0x20 /* R/W */
> #define AUPSC_AC97RST 0x24 /* R/W */
> #define AUPSC_AC97GPO 0x28 /* R/W */
> #define AUPSC_AC97GPI 0x2c /* Read only */
>
> /*
> * SMBus Protocol registers
> */
> #define AUPSC_SMBCFG 0x08 /* R/W */
> #define AUPSC_SMBMSK 0x0c /* R/W */
> #define AUPSC_SMBPCR 0x10 /* R/W */
> #define AUPSC_SMBSTAT 0x14 /* Read only */
> #define AUPSC_SMBEVNT 0x18 /* R/W */
> #define AUPSC_SMBTXRX 0x1c /* R/W */
> #define AUPSC_SMBTMR 0x20 /* R/W */
>
> #endif /* _MIPS_ALCHEMY_DEV_AUPSCREG_H_ */
>
> ------------------------------------------------------------------------
>
> /* $NetBSD$ */
>
> /*-
> * Copyright (c) 2006 Shigeyuki Fukushima.
> * All rights reserved.
> *
> * Written by Shigeyuki Fukushima.
> *
> * Redistribution and use in source and binary forms, with or without
> * modification, are permitted provided that the following conditions
> * are met:
> * 1. Redistributions of source code must retain the above copyright
> * notice, this list of conditions and the following disclaimer.
> * 2. Redistributions in binary form must reproduce the above
> * copyright notice, this list of conditions and the following
> * disclaimer in the documentation and/or other materials provided
> * with the distribution.
> * 3. The name of the author may not be used to endorse or promote
> * products derived from this software without specific prior
> * written permission.
> *
> * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
> * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
> * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
> * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
> * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> */
>
> #ifndef _MIPS_ALCHEMY_DEV_AUPSCVAR_H_
> #define _MIPS_ALCHEMY_DEV_AUPSCVAR_H_
>
> struct aupsc_attach_args {
> const char * aupsc_name;
> bus_space_tag_t aupsc_bust; /* Bus space tag */
> bus_space_handle_t aupsc_bush; /* Bus space handle */
> struct lock * aupsc_buslock; /* Bus lock */
> };
>
> #endif /* _MIPS_ALCHEMY_DEV_AUPSCVAR_H_ */
>
> ------------------------------------------------------------------------
>
> Index: alchemy/au1550.c
> ===================================================================
> RCS file: /cvsroot/src/sys/arch/mips/alchemy/au1550.c,v
> retrieving revision 1.6
> diff -u -r1.6 au1550.c
> --- alchemy/au1550.c 23 Feb 2006 03:49:28 -0000 1.6
> +++ alchemy/au1550.c 23 Feb 2006 20:24:55 -0000
> @@ -185,12 +185,12 @@
> { "augpio", { GPIO_BASE, 27 }, { -1, -1 }},
> { "augpio", { GPIO2_BASE, 16 }, { -1, -1 }},
> { "aupcmcia", { }, { -1, -1 }},
> -#if 0
> - { "usbd", { USBD_BASE }, { 24, 25 }},
> { "aupsc", { PSC0_BASE }, { 10, -1 }},
> { "aupsc", { PSC1_BASE }, { 11, -1 }},
> { "aupsc", { PSC2_BASE }, { 12, -1 }},
> { "aupsc", { PSC3_BASE }, { 13, -1 }},
> +#if 0
> + { "usbd", { USBD_BASE }, { 24, 25 }},
> { "aucrypto", { CRYPTO_BASE }, { 4, -1 }},
> #endif
> { NULL }
> Index: alchemy/include/aureg.h
> ===================================================================
> RCS file: /cvsroot/src/sys/arch/mips/alchemy/include/aureg.h,v
> retrieving revision 1.13
> diff -u -r1.13 aureg.h
> --- alchemy/include/aureg.h 20 Feb 2006 17:08:08 -0000 1.13
> +++ alchemy/include/aureg.h 23 Feb 2006 20:24:56 -0000
> @@ -132,6 +132,16 @@
> */
>
> /************************************************************************/
> +/************* Programable Serial Controller registers **************/
> +/************************************************************************/
> +
> +#define PSC0_BASE 0x011A0000
> +#define PSC1_BASE 0x011B0000
> +#define PSC2_BASE 0x010A0000
> +#define PSC3_BASE 0x010B0000
> +
> +
> +/************************************************************************/
> /********************** Ethernet MAC registers **********************/
> /************************************************************************/
>
> Index: conf/files.alchemy
> ===================================================================
> RCS file: /cvsroot/src/sys/arch/mips/conf/files.alchemy,v
> retrieving revision 1.9
> diff -u -r1.9 files.alchemy
> --- conf/files.alchemy 23 Feb 2006 03:49:29 -0000 1.9
> +++ conf/files.alchemy 23 Feb 2006 20:24:56 -0000
> @@ -59,6 +59,11 @@
> attach augpio at aubus
> file arch/mips/alchemy/dev/augpio.c augpio
>
> +# On-chip PSC
> +device aupsc
> +attach aupsc at aubus
> +file arch/mips/alchemy/dev/aupsc.c aupsc
> +
> # On-chip PCMCIA
> #
> # XXX: NOTE: As of Feb. 22, 2006, the aupcmcia bus is not quite
>
--
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134 Fax: 951 325-2191