Shigeyuki Fukushima wrote:
> Izumi Tsutsui wrote:
>   
>>> On OMS-AL400, DBAU1550 code works fine. Thanks, Garrett!
>>>       
>> Good news. How about PCI devices (wm and ehci)?
>>     
>
> Almost Ok.
> But Attaching wm0 failed. Hummmm...
>   
Please send me dmesg output.  Probably wm0 isn't in the kernel config at
least.
> kiyohara's OMS-AL400 works fine.
>
>   
>> If we can assume each PSC ports are initialized by the firmware
>> properly, we can read the protocol select register to probe
>> which protocol is selected. In this case the kernel config could be:
>>
>> aupsc* at aubus?
>> ausmbus* at aupsc?
>> smbus* at ausmbus?
>>     
>
> Is the role of aupsc device only switching/selecting protocols?
>
> Is the following kernel config bad idea??
>
> aupsc* at aubus?
> audio* at aupsc?
> spi* at aupsc?
> i2s* at aupsc?
> smbus* at aupsc?
>   
I think so.  The reason is that auaudio is e.g. very similar on the
au1550 and earlier parts, except that the au1550 implements it on a
psc.  I'd like to have a generic auaudio* module, with two different
attachment versions:

    auaudio_aubus.c -- for the earlier au1500/au1000/au1100
    auaudio_aupsc.c -- for the au1550 (and maybe au1200, i haven't
looked at the 1200 yet)

This may apply to the other modules (spi/i2s,smbus) as well.  If nothing
else, it means that you can have a limited config with only the code for
the modules you have on board in your kernel.

So lets keep aupsc really generic, with just the bits to program the PSC
registers (or possibly autodetect, but I'm not a fan of that option
primarily because I've seen bad firmware out there, and not everyone
will have YAMON) and attach the underlying "protocol-specific" drivers.

> I will attach current-working codes.
> Please review it.
>   
Looks reasonable.  I don't have any objections if you want to commit
this, as it isn't in any default configs yet.  (C.F. my PCMCIA commits.)

    -- Garrett
>   
>> But we should implement smbus and RTC drivers first
>> because logical layers for device configuration could be
>> changed later, IMHO.
>>     
>
> Thank you for your advice.
>
>
> FYI:
> OMS-AL400 boot log is the following:
>
> YAMON> go 80100000
> MIPS32/64 params: cpu arch: 32
> MIPS32/64 params: TLB entries: 32
> MIPS32/64 params: Icache: line = 32, total = 16384, ways = 4
>                  sets = 128
> MIPS32/64 params: Dcache: line = 32, total = 16384, ways = 4
>                  sets = 128
>   picache_stride    = 4096
>   picache_loopcount = 4
>   pdcache_stride    = 4096
>   pdcache_loopcount = 4
>   Dcache is coherent
>   Icache is coherent against Dcache
> Memory size: 0x08000000
> Loaded initial symtab at 0x803832b4, strtab at 0x80398768, # entries 5349
> Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
> 2005, 2006
>     The NetBSD Foundation, Inc.  All rights reserved.
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>     The Regents of the University of California.  All rights reserved.
>
> NetBSD 3.99.15 (OMSAL400) #25: Fri Feb 24 01:01:42 JST 2006
>
> root@netbsd.griffinet.dyndns.org:/opt/build/objdir.mipsel/sys/arch/evbmips/compile/OMSAL400
> Plathome Open Micro Sever AL400/AMD Alchemy Au1550
> total memory = 128 MB
> avail memory = 120 MB
> mainbus0 (root)
> cpu0 at mainbus0: 396.00MHz (hz cycles = 773438, delay divisor = 396)
> cpu0: Alchemy Au1550 (Rev 2 core) (0x3030200) Rev. 0 with software
> emulated floating point
> cpu0: 16KB/32B 4-way set-associative L1 Instruction cache, 32 TLB entries
> cpu0: 16KB/32B 4-way set-associative write-back L1 Data cache
> obio0 at mainbus0
> aubus0 at mainbus0
> aucom0 at aubus0 addr 0x11100000 irq 0: Au1X00 UART, working fifo
> aucom0: console
> aucom1 at aubus0 addr 0x11200000 irq 8: Au1X00 UART, working fifo
> aucom2 at aubus0 addr 0x11400000 irq 9: Au1X00 UART, working fifo
> aurtc0 at aubus0 addr 0x0: Au1X00 programmable clock
> aumac0 at aubus0 addr 0x10500000 irq 27: Au1X00 10/100 Ethernet
> aumac0: Ethernet address 00:0a:85:02:00:bf
> lxtphy0 at aumac0 phy 0: LXT971/2 10/100 media interface, rev. 2
> lxtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
> aumac1 at aubus0 addr 0x10510000 irq 28: Au1X00 10/100 Ethernet
> aumac1: Ethernet address 00:0a:85:02:10:bf
> ohci0 at aubus0 addr 0x14020000 irq 26: Alchemy OHCI
> ohci0: OHCI version 1.0
> usb0 at ohci0: USB revision 1.0
> uhub0 at usb0
> uhub0: vendor 0x0000 OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
> uhub0: 2 ports with 2 removable, self powered
> aupci0 at aubus0 addr 0x14005000: Alchemy Host-PCI Bridge, 66MHz
> pci0 at aupci0 bus 0
> pci0: i/o space, memory space enabled
> ohci1 at pci0 dev 2 function 0: NEC USB Host Controller (rev. 0x43)
> ohci1: interrupting at irq 5
> ohci1: OHCI version 1.0
> usb1 at ohci1: USB revision 1.0
> uhub1 at usb1
> uhub1: NEC OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
> uhub1: 3 ports with 3 removable, self powered
> ohci2 at pci0 dev 2 function 1: NEC USB Host Controller (rev. 0x43)
> ohci2: interrupting at irq 5
> ohci2: OHCI version 1.0
> usb2 at ohci2: USB revision 1.0
> uhub2 at usb2
> uhub2: NEC OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
> uhub2: 2 ports with 2 removable, self powered
> ehci0 at pci0 dev 2 function 2: NEC USB Host Controller (rev. 0x04)
> ehci0: interrupting at irq 5
> ehci0: BIOS has given up ownership
> ehci0: EHCI version 1.0
> ehci0: companion controllers, 3 ports each: ohci1 ohci2
> usb3 at ehci0: USB revision 2.0
> uhub3 at usb3
> uhub3: NEC EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
> uhub3: 5 ports with 5 removable, self powered
> wm0 at pci0 dev 3 function 0: Intel i82541GI 1000BASE-T Ethernet, rev. 5
> wm0: unable to map device registers
> wm1 at pci0 dev 4 function 0: Intel i82541GI 1000BASE-T Ethernet, rev. 5
> wm1: interrupting at irq 1
> wm1: Ethernet address 00:0a:85:02:50:46
> igphy0 at wm1 phy 1: Intel IGP01E1000 Gigabit PHY, rev. 0
> igphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
> 1000baseT-FDX, auto
> augpio0 at aubus0 addr 0x11900100: Alchemy GPIO, primary block
> gpio0 at augpio0: 27 pins
> augpio1 at aubus0 addr 0x11700000: Alchemy GPIO, secondary block
> gpio1 at augpio1: 16 pins
> aupsc0 at aubus0 addr 0x11a0000 irq 10: Alchemy PSC
> aupsc1 at aubus0 addr 0x11b0000 irq 11: Alchemy PSC
> aupsc2 at aubus0 addr 0x10a0000 irq 12: Alchemy PSC
> aupsc3 at aubus0 addr 0x10b0000 irq 13: Alchemy PSC
> root device:
>
>   
> ------------------------------------------------------------------------
>
> /* $NetBSD$ */
>
> /*-
>  * Copyright (c) 2006 Shigeyuki Fukushima.
>  * All rights reserved.
>  *
>  * Written by Shigeyuki Fukushima.
>  *
>  * Redistribution and use in source and binary forms, with or without
>  * modification, are permitted provided that the following conditions
>  * are met:
>  * 1. Redistributions of source code must retain the above copyright
>  *    notice, this list of conditions and the following disclaimer.
>  * 2. Redistributions in binary form must reproduce the above
>  *    copyright notice, this list of conditions and the following
>  *    disclaimer in the documentation and/or other materials provided
>  *    with the distribution.
>  * 3. The name of the author may not be used to endorse or promote
>  *    products derived from this software without specific prior
>  *    written permission.
>  *
>  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
>  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
>  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
>  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
>  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
>  * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
>  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
>  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
>  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>  */
>
> #ifndef _MIPS_ALCHEMY_DEV_AUPSCREG_H_
> #define	_MIPS_ALCHEMY_DEV_AUPSCREG_H_
>
> /*
>  * PSC registers (offset from PSCn_BASE).
>  */
>
> /* psc_sel: PSC clock and protocol select
>  *   CLK [5:4]
>  *     00 = pscn_intclk (for SPI, SMBus, I2S Master[PSC3 Only])
>  *     01 = PSCn_EXTCLK (for SPI, SMBus, I2S Master)
>  *     10 = PSCn_CLK    (for AC97, I2S Slave)
>  *     11 = Reserved
>  *   PS [2:0]
>  *     000 = Protocol disable
>  *     001 = Reserved
>  *     010 = SPI mode
>  *     011 = I2S mode
>  *     100 = AC97 mode
>  *     101 = SMBus mode
>  *     11x = Reserved
>  */
> #define	AUPSC_SEL			0x00	/* R/W */
> #  define	AUPSC_SEL_CLK(x)	((x & 0x03) << 4) /* CLK */
> #  define	AUPSC_SEL_PS(x)		(x & 0x07)
> #  define	AUPSC_SEL_DISABLE	0
> #  define	AUPSC_SEL_SPI		2
> #  define	AUPSC_SEL_I2S		3
> #  define	AUPSC_SEL_AC97		4
> #  define	AUPSC_SEL_SMBUS		5
>
> /* psc_ctrl: PSC control
>  *  ENA [1:0]
>  *    00 = Disable/Reset
>  *    01 = Reserved
>  *    10 = Suspend
>  *    10 = Enable
>  */
> #define	AUPSC_CTRL			0x04	/* R/W */
> #  define	AUPSC_CTRL_ENA(x)	(x & 0x03)
>
> /* 0x0008 - 0x002F: Protocol-specific registers */
>
> /* PSC registers size */
> #define	AUPSC_SIZE			0x2f
>
>
> /*
>  * SPI Protocol registers
>  */
> #define	AUPSC_SPICFG			0x08	/* R/W */
> #define	AUPSC_SPIMSK			0x0c	/* R/W */
> #define	AUPSC_SPIPCR			0x10	/* R/W */
> #define	AUPSC_SPISTAT			0x14	/* Read only */
> #define	AUPSC_SPIEVNT			0x18	/* R/W */
> #define	AUPSC_SPITXRX			0x1c	/* R/W */
> /* #include <mips/alchemy/dev/spireg.h> */
>
> /*
>  * I2S Protocol registers
>  */
> #define	AUPSC_I2SCFG			0x08	/* R/W */
> #define	AUPSC_I2SMSK			0x0c	/* R/W */
> #define	AUPSC_I2SPCR			0x10	/* R/W */
> #define	AUPSC_I2SSTAT			0x14	/* Read only */
> #define	AUPSC_I2SEVNT			0x18	/* R/W */
> #define	AUPSC_I2STXRX			0x1c	/* R/W */
> #define	AUPSC_I2SUDF			0x20	/* R/W */
> /* #include <mips/alchemy/dev/i2sreg.h> */
>
> /*
>  * AC97 Protocol registers
>  */
> #define	AUPSC_AC97CFG			0x08	/* R/W */
> #define	AUPSC_AC97MSK			0x0c	/* R/W */
> #define	AUPSC_AC97PCR			0x10	/* R/W */
> #define	AUPSC_AC97STAT			0x14	/* Read only */
> #define	AUPSC_AC97EVNT			0x18	/* R/W */
> #define	AUPSC_AC97TXRX			0x1c	/* R/W */
> #define	AUPSC_AC97CDC			0x20	/* R/W */
> #define	AUPSC_AC97RST			0x24	/* R/W */
> #define	AUPSC_AC97GPO			0x28	/* R/W */
> #define	AUPSC_AC97GPI			0x2c	/* Read only */
> /* #include <mips/alchemy/dev/ac97reg.h> */
>
> /*
>  * SMBus Protocol registers
>  */
> #define	AUPSC_SMBCFG			0x08	/* R/W */
> #define	AUPSC_SMBMSK			0x0c	/* R/W */
> #define	AUPSC_SMBPCR			0x10	/* R/W */
> #define	AUPSC_SMBSTAT			0x14	/* Read only */
> #define	AUPSC_SMBEVNT			0x18	/* R/W */
> #define	AUPSC_SMBTXRX			0x1c	/* R/W */
> #define	AUPSC_SMBTMR			0x20	/* R/W */
> #include <mips/alchemy/dev/smbusreg.h>
>
> #endif	/* _MIPS_ALCHEMY_DEV_AUPSCREG_H_ */
>   
> ------------------------------------------------------------------------
>
> /* $NetBSD$ */
>
> /*-
>  * Copyright (c) 2006 Shigeyuki Fukushima.
>  * All rights reserved.
>  *
>  * Written by Shigeyuki Fukushima.
>  *
>  * Redistribution and use in source and binary forms, with or without
>  * modification, are permitted provided that the following conditions
>  * are met:
>  * 1. Redistributions of source code must retain the above copyright
>  *    notice, this list of conditions and the following disclaimer.
>  * 2. Redistributions in binary form must reproduce the above
>  *    copyright notice, this list of conditions and the following
>  *    disclaimer in the documentation and/or other materials provided
>  *    with the distribution.
>  * 3. The name of the author may not be used to endorse or promote
>  *    products derived from this software without specific prior
>  *    written permission.
>  *
>  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
>  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
>  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
>  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
>  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
>  * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
>  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
>  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
>  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>  */
>
> #include <sys/cdefs.h>
> __KERNEL_RCSID(0, "$NetBSD$");
>
> #include "locators.h"
>
> #include <sys/param.h>
> #include <sys/systm.h>
> #include <sys/device.h>
> #include <sys/errno.h>
>
> #include <machine/bus.h>
> #include <machine/cpu.h>
>
> #include <mips/alchemy/include/aubusvar.h>
> #include <mips/alchemy/include/aureg.h>
> #include <mips/alchemy/dev/aupscreg.h>
> #include <mips/alchemy/dev/aupscvar.h>
>
> struct aupsc_softc {
> 	struct device		sc_dev;
> 	bus_space_tag_t		sc_bst;
> 	bus_space_handle_t	sc_bsh;
> 	int			sc_pscsel;
> 	struct aupsc_ac97	sc_ac97;
> 	struct aupsc_i2s	sc_i2s;
> 	struct aupsc_spi	sc_spi;
> 	struct aupsc_smbus	sc_smbus;
> };
>
> static int	aupsc_match(struct device *, struct cfdata *, void *);
> static void	aupsc_attach(struct device *, struct device *, void *);
>
> CFATTACH_DECL(aupsc, sizeof(struct aupsc_softc),
>     aupsc_match, aupsc_attach, NULL, NULL);
>
> static int
> aupsc_match(struct device *parent, struct cfdata *cf, void *aux)
> {
> 	struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
>
> 	if (strcmp(aa->aa_name, cf->cf_name) != 0)
> 		return 0;
>
> 	return 1;
> }
>
> static void
> aupsc_attach(struct device *parent, struct device *self, void *aux)
> {
> 	struct aupsc_softc *sc = (struct aupsc_softc *)self;
> 	struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
>
> 	sc->sc_bst = aa->aa_st;
> 	if (bus_space_map(sc->sc_bst, aa->aa_addrs[0],
> 			AUPSC_SIZE, 0, &sc->sc_bsh) != 0) {
> 		printf(": unbale to map device registers\n");
> 		return;
> 	}
>
> 	sc->sc_pscsel = AUPSC_SEL_DISABLE;
>
> 	aprint_normal(": Alchemy PSC\n");
> }
>   
> ------------------------------------------------------------------------
>
> /* $NetBSD$ */
>
> /*-
>  * Copyright (c) 2006 Shigeyuki Fukushima.
>  * All rights reserved.
>  *
>  * Written by Shigeyuki Fukushima.
>  *
>  * Redistribution and use in source and binary forms, with or without
>  * modification, are permitted provided that the following conditions
>  * are met:
>  * 1. Redistributions of source code must retain the above copyright
>  *    notice, this list of conditions and the following disclaimer.
>  * 2. Redistributions in binary form must reproduce the above
>  *    copyright notice, this list of conditions and the following
>  *    disclaimer in the documentation and/or other materials provided
>  *    with the distribution.
>  * 3. The name of the author may not be used to endorse or promote
>  *    products derived from this software without specific prior
>  *    written permission.
>  *
>  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
>  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
>  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
>  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
>  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
>  * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
>  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
>  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
>  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>  */
>
> #ifndef _MIPS_ALCHEMY_DEV_AUPSCVAR_H_
> #define	_MIPS_ALCHEMY_DEV_AUPSCVAR_H_
>
> #include <dev/i2c/i2cvar.h>
> #include <dev/i2c/i2c_bitbang.h>
>
> struct aupsc_ac97 {
> };
>
> struct aupsc_i2s {
> };
>
> struct aupsc_spi {
> };
>
> struct aupsc_smbus {
> 	uint8_t			i2c_txen;
> 	struct i2c_controller	i2c_ctl;
> 	struct i2c_bitbang_ops	i2c_bops;
> 	struct lock		i2c_buslock;
> };
>
> #endif	/* _MIPS_ALCHEMY_DEV_AUPSCVAR_H_ */
>   


-- 
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134  Fax: 951 325-2191