Byron.Servies@Sun.COM wrote:

> I found the following on an internal web site and received permission to 
> publish it.

Yeah, this is an evidence which I'd like to see..

> I'm also looking for additional information on the Qube2/RaQ2 
> internally.  There was a question recently about how the PCI interrupt 
> pins were connected, for example, and if I can find someone who still 
> has the schematics, I'll ask.

I also wonder if the firmware could handle multifunction PCI devices
or PCI bridges, which could use PIN B,C and D.

> Qube 1:
> H/W int0 : Galileo CPU Interrupt (pin 61)
> H/W int1 : Coprocessor Interrupt
> H/W int2 : Ethernet Int.
> H/W int3 : Spare
> H/W int4 : Via Intr (pin 145)
> H/W int5 : Galileo PCI Interrupt (pin 196)
> H/W NMI : Via NMI (Pin 146)

Hmm, then maybe we need the following patch for Qube2700:

---
Index: pci/pci_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/pci/pci_machdep.c,v
retrieving revision 1.24
diff -u -r1.24 pci_machdep.c
--- pci/pci_machdep.c	22 Aug 2006 21:42:19 -0000	1.24
+++ pci/pci_machdep.c	15 Feb 2007 13:08:35 -0000
@@ -156,12 +156,19 @@
 	 * directly to the CPU.
 	 */
 
-	if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A)
-		*ihp = 16 + 1;
-	else if (bus == 0 && dev == 12 && pin == PCI_INTERRUPT_PIN_A)
-		*ihp = 16 + 2;
-	else
-		*ihp = line;
+	if (cobalt_id == COBALT_ID_QUBE2700) {
+		if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A)
+			*ihp = 16 + 2;
+		else
+			*ihp = line;
+	} else {
+		if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A)
+			*ihp = 16 + 1;
+		else if (bus == 0 && dev == 12 && pin == PCI_INTERRUPT_PIN_A)
+			*ihp = 16 + 2;
+		else
+			*ihp = line;
+	}
 
 	return 0;
 }

---

> The Galileo interrupt on line 5 is odd. This is supposed to be directed
> at the PCI bus, in case the
> procesor wants to generate an interrupt on some PCI device. Anyone who
> wants to suggest a
> reason for this configuration is welcome.

AFAIK, CPU INT5 can be configured to use external hardware interrupt
or internal clock interrupt, and Rm52xx on cobalt uses INT5 for
internal clocks. I have no idea if it's intended, but maybe
that's why original Linux kernel uses timer in Galileo for
clock interrupt.

> Cube-1
> IRQ 3 : SMI
> IRQ 4 : Serial Interrupt
> IRQ 6 : rlng Interrupt ??? (ringInt?)
> IRQ 9 : PCI Slot Interrupt
> IRQ 14 : 2nd IDE Interrupt

Hmm, no primary IDE interrupt on Qube2700, or pasto?

> Software PCI configuration:
> PCI_BASE_ADDRESS_SPACE_IO means alloc from 0x10108000
> else alloc from membase 0x12000000

FYI, NetBSD/cobalt uses I/O space from 0x10001000 to 0x11ffffff
and it seems to work.
---
Izumi Tsutsui